Senior Memory Circuit Design Engineer

Broadcom Inc.; Mendota Heights (MN); On-site; USD 105,000 - 176,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) with company matching

ESPP

Paid holidays, sick leave and vacation

Job summary

Broadcom Inc. is seeking a Staff Memory Circuit Design Engineer to join the Central Engineering Group, focusing on memory compilers and custom macros using cutting-edge process technology.

You will analyze architectures, design blocks at gate or transistor level, run transistor-level simulations, lay out leaves, and optimize timing and power in silicon. The role requires a BS in Electrical Engineering with 8+ years of related experience, strong memory design knowledge, and proficiency in

Qualifications

• BS in Electrical Engineering with 8+ years of related experience.
• Strong knowledge in memory compiler development or custom digital circuits.
• Deep understanding of transistor-level circuit behavior and device physics.
• Good understanding of signal integrity, EM/IR, and reliability analysis.
• Familiarity with test setups and silicon testing.
• Proficient in running simulators and writing automation scripts; Python is a plus.

Responsibilities

• Analyze memory architectures and evaluate tradeoffs.
• Design and build memory blocks at gate or transistor level.
• Simulate and analyze circuit designs with transistor-level simulators.
• Extract layout and perform post-layout simulations and verification.
• Floorplan physical implementation and leafcell layout integration.
• Integrate characterization flow to extract timing and power information.
• Develop scripts to automate characterization, simulations, and verification.
• Specify and verify memory models and silicon test plans.
• Help debug silicon issues.

Skills

Memory compiler dev

Python

Circuit design

DFT concepts

Education

B.S. in Electrical Engineering

Tools

Circuit simulators

Automation scripts

Job description

Broadcom Inc. is seeking a Staff Memory Circuit Design Engineer to join the Central Engineering Group, focusing on memory compilers and custom macros using cutting-edge process technology.

You will analyze architectures, design blocks at gate or transistor level, run transistor-level simulations, lay out leaves, and optimize timing and power in silicon. The role requires a BS in Electrical Engineering with 8+ years of related experience, strong memory design knowledge, and proficiency in