Memory System Designer and Place and Route Engineer

Broadcom Inc.; Mendota Heights (MN); On-site; USD 110,000 - 176,000; Full time

Job summary

Broadcom Inc. in Mendota Heights is seeking a Memory System Designer and Place & Route Engineer to contribute to memory subsystem design, architecture, and RTL implementations. The role requires hands-on RTL, place & route, and design-closure expertise in a fast-paced environment.

The candidate should have 8+ years of relevant experience, strong Verilog and Python skills, and experience with STA/DRC/EMIR tools to ensure high-quality design closures and robust memory blocks.

Qualifications

• Minimum 8 years of relevant experience in memory subsystem design.
• Bachelor's degree in Electrical Engineering required.
• Strong RTL design and debugging skills; place & route and design closure experience required.

Responsibilities

• Architect and design memory subsystems.
• Implement RTL of subsystem designs.
• Place and route (physical design).
• Design closure: timing, DRC, LVS, EM/IR, etc.
• Gate netlist synthesis.

Skills

Verilog RTL

Place & Route

STA/DRC/EMIR

Python scripting

Synthesis tools

Memory behavior

Automation scripts

Leadership

Communication

Multitasking

Education

Bachelor's degree in Electrical Engineering

Tools

Verilog

STA/DRC tools

Synthesis tools

Python

Job description

## Memory System Designer and Place and Route EngineerApply: USA-Mendota Heights-Northland: Full time: Posted Today: R027233**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **Job Description:**We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.******Job Responsibilities*** Architect and design memory subsystems* Implement RTL of subsystem designs* Place and route (physical design)* Design closure: timing, DRC, LVS, EM/IR, etc.* Gate netlist synthesis**Skill Set Required*** Strong design skills* Ability to write and debug Verilog RTL code* Place and route expertise* Proficient in running STA, DRC, EM/IR tools, and attaining design closure* Ability to code in Python* Good understanding of synthesis tools and running synthesis* Capable of running and debugging logical equivalency checkers* Familiar with memory behavior* Proficient in writing automation scripts, and tools savvy* Good communication, interpersonal, and leadership skills* Motivated, self-driven, and good at multitasking **Compensation and Benefits** The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. **Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.**