Senior DRAM Systems Architect – Memory Innovation

Micron Technology, Inc

San Jose (CA)

On-site

USD 177,000 - 387,000

Full time

14 days+

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Benefits offered by this job

Medical insurance
Dental insurance
Vision insurance
Paid time off
Paid holidays
Paid family leave
Income protection

Job summary

Micron Technology, Inc. is seeking a Systems Design Engineering SMTS to drive next-generation memory system builds with focus on performance, capacity, and telemetry.

You will coordinate silicon, package, module, board, and system-level optimization, translating system needs into silicon while coordinating with customers and executives. The role demands a strong background in DRAM timing, power, and reliability, with the ability to influence industry standards and provide leadership across

Qualifications

  • Bachelor’s degree or relevant equivalent experience in EE, CE, CS, or a related field.
  • Extensive hands‑on experience in DRAM or memory systems architecture.
  • Deep understanding of DRAM timing, signaling, power, and reliability mechanisms.

Responsibilities

  • Define next-generation memory system builds focusing on performance, capacity, RAS, and telemetry.
  • Lead cross‑stack co‑optimization spanning silicon, package, module, board, and system.
  • Architect sophisticated RAS and telemetry features and translate system needs into silicon.
  • Drive long‑range memory technology strategy and influence industry standards.
  • Act as a senior technical liaison to customers, executives, and partners.

Skills

DRAM Architecture
Memory Systems
System Co-Optimization

Education

Bachelor's degree or equivalent (EE/CE/CS)

Job description

Micron Technology, Inc. is seeking a Systems Design Engineering SMTS to drive next-generation memory system builds with focus on performance, capacity, and telemetry.

You will coordinate silicon, package, module, board, and system-level optimization, translating system needs into silicon while coordinating with customers and executives. The role demands a strong background in DRAM timing, power, and reliability, with the ability to influence industry standards and provide leadership across

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