Memory Packaging Architect for Edge & Data Center AI

Micron Technology, Inc; Boise (ID); On-site; USD 143,000 - 398,000; Full time

Job summary

Micron Technology, Inc in Boise, ID is seeking a Product Development Engineer 5 - Hardware Engineering MTS to define next-generation memory packaging architectures and to drive cross‑stack optimization across silicon, package, board, and system.

You will work with silicon, system design teams and customers, apply AI‑based multi‑physics methods, and help shape long‑term packaging strategy for edge‑AI and data center memory products.

Qualifications

• Master’s degree or equivalent practical experience in EE, CE, CS, or related field.
• 6+ years of extensive hands-on experience in memory systems package design, signaling, IO design, PDN design.
• Deep understanding of memory timing, signaling, power, package process technology.

Responsibilities

• Define next-generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance.
• Lead cross-stack co-optimization across silicon, package, board, and system with package-centric solutions approach.
• Drive long-term memory technology packaging strategy and influence industry standards.
• Work closely with silicon and system design teams and customers for next generation and long-term disruptive solutions to boost speed performance for edge‑AI and datacenter memory products.
• Serve as a technical interface to internal partners, customers, BUs, senior leaders.
• Develop AI based multi-physics solutions for efficiency gains.

Skills

Memory systems

AI / LLMs in engineering

Cross-stack optimization

Education

Master's degree in EE/CE/CS or related field

Tools

Cadence

Siemens

Ansys

Job description

Micron Technology, Inc in Boise, ID is seeking a Product Development Engineer 5 - Hardware Engineering MTS to define next-generation memory packaging architectures and to drive cross‑stack optimization across silicon, package, board, and system.

You will work with silicon, system design teams and customers, apply AI‑based multi‑physics methods, and help shape long‑term packaging strategy for edge‑AI and data center memory products.