DRAM Memory Design Engineer — Optimize Circuits & Silicon

Micron; Boise (ID); On-site; USD 110,000 - 170,000; Full time

Job summary

Micron Technology in Boise, Idaho is seeking a Semiconductor Design Engineer focused on memory circuit design, layout, and validation. You will design and optimize memory circuits, run SPICE/Verilog simulations, and collaborate on architecture choices to ensure silicon success.

Responsibilities include design, layout, simulation, and test-chip activities, plus contributing to AI-enabled improvements in design workflows.

Qualifications

• Bachelor's degree in Electrical Engineering (BSEE) or higher, or equivalent experience.
• Basic understanding of memory array architectures, circuits, and operation.
• Strong understanding of circuit simulation setup, analysis, and debug techniques.
• Strong written and verbal communication skills with the ability to convey technical concepts to peers and management.
• Familiarity with semiconductor device fundamentals and integrated circuit design principles.

Responsibilities

• Design, layout, and optimize memory circuits with a focus on performance, power, area, and manufacturability.
• Perform circuit simulation and analysis using industry-standard tools such as SPICE and Verilog to validate circuit functionality.
• Develop and support schematic blocks including memory arrays, control logic, address decoders, datapaths, and internal test circuitry.
• Evaluate design architecture tradeoffs and incorporate layout parasitics to ensure robust circuit operation and silicon success.
• Drive innovation through test chip development, silicon validation, and AI-enabled improvements to design methodologies and workflows.

Job description

Micron Technology in Boise, Idaho is seeking a Semiconductor Design Engineer focused on memory circuit design, layout, and validation. You will design and optimize memory circuits, run SPICE/Verilog simulations, and collaborate on architecture choices to ensure silicon success.

Responsibilities include design, layout, simulation, and test-chip activities, plus contributing to AI-enabled improvements in design workflows.