Block-Level Layout Engineer — Memory Tech Impact

Micron; Boise (ID); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Benefits guide

Job summary

Micron Technology is seeking a Layout Engineer to shape block-level layouts and guide physical design strategy for DRAM products. You will build layouts in Cadence Virtuoso, ensure DRC/LVS compliance, and support post-layout verification across global teams.

Join a world-leader in memory technologies and contribute to high‑reliability designs, working with cross-site groups to drive layout goals and optimize performance across generations of devices.

Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with cross-site teams.

Responsibilities

• Build block-level layouts in Cadence Virtuoso including floorplanning, placement, routing, and optimization.
• Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy.
• Ensure DRC, LVS, density, and reliability compliance.
• Support parasitic extraction, post-layout verification, and ECO activities.
• Create partial custom layouts for selected device-level or small analog blocks.

Skills

Cadence Virtuoso

Physical layout

DRC/LVS

Cross-site collaboration

Tools

Cadence Virtuoso

Job description

Micron Technology is seeking a Layout Engineer to shape block-level layouts and guide physical design strategy for DRAM products. You will build layouts in Cadence Virtuoso, ensure DRC/LVS compliance, and support post-layout verification across global teams.

Join a world-leader in memory technologies and contribute to high‑reliability designs, working with cross-site groups to drive layout goals and optimize performance across generations of devices.