Layout Engineer, DEG

Micron Technology; Boise (ID); Sur place; USD 80 000 - 100 000; Plein temps

Résumé du poste

Micron Technology, Inc is seeking a dedicated Layout Engineer in Boise, Idaho to work on the physical design foundations behind their memory technologies. You will build block-level layouts, apply various layout methods, and ensure compliance with key design standards.

The ideal candidate has experience with Cadence Virtuoso, understands DRC and LVS, and is able to collaborate with global engineering teams. This role offers a chance to work on cutting-edge memory solutions.

Qualifications

• Experience performing physical layout in Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with teams.

Responsabilités

• Build block-level layouts in Cadence Virtuoso including placement and routing.
• Ensure DRC, LVS, density, and reliability compliance.
• Support parasitic extraction and post-layout verification.

Connaissances

Cadence Virtuoso

DRC and LVS compliance

Layout design and optimization

Description du poste

Req ID: JR103399 Layout Engineer, DEG

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our layout engineering team drives the physical design foundations behind Micron’s industry‑leading memory technologies. We work closely across global design, CAD, and verification groups, solving sophisticated challenges and enabling the performance and scalability our products rely on!

Responsibilities

• Build block‑level layouts in Cadence Virtuoso including floorplanning, placement, routing, and optimization
• Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy
• Ensure DRC, LVS, density, and reliability compliance
• Support parasitic extraction, post‑layout verification, and ECO activities
• Create partial custom layouts for selected device‑level or small analog blocks

Minimum Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools
• Familiarity with DRC, LVS, physical verification, and reliability checks
• Ability to plan, document, and review layout goals with cross‑site teams

Preferred Qualifications

• Experience with DRAM, memory circuits, or large hierarchical designs
• Background in parasitic extraction flows and post‑layout optimization
• Hands‑on experience with partial custom layout for devices or small analog circuits
• Strong communication skills supporting global engineering teams

Job Profile(s)

• Layout/Mask Designer E2

Relocation Level: TBD

Equal Opportunity Employer Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.