Memory Controller Verification Engineer II (UVM)

Cadence; Austin (TX); On-site; USD 90,000 - 130,000; Full time

Job summary

Cadence invites a Verification Engineer to join the Memory Controller development team in Austin. The role focuses on leading verification efforts, enhancing the existing UVM-based environment, and validating diverse customer configurations during regressions.

The candidate will ensure adherence to the team's technical and quality requirements and contribute to coverage and defect analyses. Austin-based position with opportunities to impact next-gen IP verifications.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent.
• 2–3 years of relevant design verification experience.
• Strong background in functional verification fundamentals and environment development.
• UVM-based verification environment development required.
• AXI/CHI-E and DDR memory experience desirable.

Responsibilities

• Lead verification effort for Cadence Memory Controller IP.
• Work with existing functional verification environment to add features.
• Ensure multiple customer configurations pass verification regressions.
• Provide support to customers for verification environment issues.
• Contribute to functional and code coverage; align design with quality metrics.

Skills

Functional verification

UVM

Environment planning

Test plan

Memory interfaces (AXI/CHI-E)

DDR memory experience

Memory controller verification

Education

BS/MS - Electrical / Computer Engineering

Job description

Cadence invites a Verification Engineer to join the Memory Controller development team in Austin. The role focuses on leading verification efforts, enhancing the existing UVM-based environment, and validating diverse customer configurations during regressions.

The candidate will ensure adherence to the team's technical and quality requirements and contribute to coverage and defect analyses. Austin-based position with opportunities to impact next-gen IP verifications.