Design Engineer II

Cadence; Austin (TX); On-site; USD 90,000 - 130,000; Full time

Job summary

Cadence invites a Verification Engineer to join the Memory Controller development team in Austin. The role focuses on leading verification efforts, enhancing the existing UVM-based environment, and validating diverse customer configurations during regressions.

The candidate will ensure adherence to the team's technical and quality requirements and contribute to coverage and defect analyses. Austin-based position with opportunities to impact next-gen IP verifications.

Qualifications

• BS/MS in Electrical or Computer Engineering or equivalent.
• 2–3 years of relevant design verification experience.
• Strong background in functional verification fundamentals and environment development.
• UVM-based verification environment development required.
• AXI/CHI-E and DDR memory experience desirable.

Responsibilities

• Lead verification effort for Cadence Memory Controller IP.
• Work with existing functional verification environment to add features.
• Ensure multiple customer configurations pass verification regressions.
• Provide support to customers for verification environment issues.
• Contribute to functional and code coverage; align design with quality metrics.

Skills

Functional verification

UVM

Environment planning

Test plan

Memory interfaces (AXI/CHI-E)

DDR memory experience

Memory controller verification

Education

BS/MS - Electrical / Computer Engineering

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.

The position is based in Austin.

Position Requirements

• BS/MS - Electrical / Computer Engineering
• At least 2-3 years of relevant experience including design verification experience.
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• UVM based functional verification environment development is required.
• AXI and/or CHI-E, DDR Memory experience is highly desirable.
  

Memory controller verification experience is desirable.

As a Verification Engineer for Memory Controller development team, you will lead the verification effort and contribute to the functional verification of the Cadence's Memory Controller IP. This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.

The position is based in Austin.

Position Requirements

• BS/MS - Electrical / Computer Engineering
• At least 2-3 years of relevant experience including design verification experience.
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• UVM based functional verification environment development is required.
• AXI and/or CHI-E experience is highly desirable.
  

Memory controller verification experience is desirable.

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