Lead Processor Verification Architect

Cadence

San Jose (CA)

On-site

USD 186,000 - 345,000

Full time

3 days ago

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Job summary

Cadence is seeking a Design Verification Team Director in California or Austin to lead the Processor Verification team. You will verify microprocessor cores and peripherals, craft verification plans, and implement testbenches with coverage closure.

You will coordinate with DV/Arch/Design/FW teams and report on a 7-10 engineer group. The role demands 17+ years in design verification, a BS in EE/CE, strong leadership, and deep knowledge of SystemVerilog/UVM, plus scripting skills (Perl/Unix

Qualifications

17+ years of design verification experience.
BS (or higher) in EE/Computer Engineering.
Proven experience at leading/managing a team.
Strong managerial, leadership and interpersonal skills.
Excellent knowledge of computer architecture and verification fundamentals.
Thorough understanding of SystemVerilog, UVM, and related languages.
Exposure to scripting languages like Perl, Unix shell or similar.

Responsibilities

Crafting verification plans and executing them to verify highly complex CPU designs.
Implement simulation or emulation testbenches and diagnostics to meet goals.
Responsible for coverage collection and closure.
Work with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope.
Tracking and reporting the work of 7-10 engineers.