Memory Architect - SRAM & CRAM for High-Performance SoCs

Lattice Semiconductor; San Jose (CA); Hybrid; USD 224,000 - 273,000; Full time

Job summary

Lattice Semiconductor in San Jose, CA invites applications for a Senior Memory Designer to lead design of high-speed SRAM and CRAM, drive architectures, and ensure robust verification.

This role spans the full memory design flow from architecture to timing and model generation, collaborating with architecture and design teams to hit performance, power and area targets.

A BS in EE is required; MS/PhD is preferred with 10+ years in memory design and strong problem-solving and communication skills.

Qualifications

• Bachelor's degree in electrical engineering or related field; Master or PhD preferred.
• 10+ years of memory design, verification, validation, and integration.
• Strong knowledge of custom memory design, high speed and low power techniques.
• Familiarity with variation-aware design in advanced semiconductor technologies.

Responsibilities

• Lead design and development of custom memory blocks for SRAM and CRAM.
• Develop memory architectures and implement in FinFET/nanometer CMOS processes.
• Perform schematic capture, simulation, and margin verification.
• Oversee layout planning and ensure pitch-matched memory layouts.
• Collaborate with architecture and design teams to hit memory PPA and yield targets.
• Manage full embedded memory design flow from architecture to model generation.

Skills

Memory design

High speed design

Low power design

Architecture

Verification

Layout planning

PPA targets

Communication

Education

Bachelor's degree in electrical engineering

Master's or PhD preferred

Job description

Lattice Semiconductor in San Jose, CA invites applications for a Senior Memory Designer to lead design of high-speed SRAM and CRAM, drive architectures, and ensure robust verification.

This role spans the full memory design flow from architecture to timing and model generation, collaborating with architecture and design teams to hit performance, power and area targets.

A BS in EE is required; MS/PhD is preferred with 10+ years in memory design and strong problem-solving and communication skills.