Low-Power SoC ASIC Design Engineer

QUALCOMM, Inc.; Santa Clara (CA); On-site; USD 190,000 - 285,000; Full time

Benefits offered by this job

Competitive benefits package

RSU grants

Annual bonus program

Job summary

Qualcomm Atheros, Inc. in Santa Clara, CA is seeking a Design Engineer (Low Power) to drive low power ASIC design from specification through silicon bring-up. The role emphasizes ARM IP-based full chip debugging, power intent, and multi-domain clocking within a fast-paced wireless technology team.

You will develop architectural specifications, own the power design flow, perform power measurements, and collaborate with verification to achieve timing closure and robust silicon deployment.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 6+ years of ASIC design/verification experience, or higher degrees with corresponding years.
• Experience in low power micro-architecture, Power Intent/Implementation, power estimation and analysis.
• Proficiency in SoC debug, silicon bring-up, and ARM IP based full chip debugging preferred.

Responsibilities

• Develop low power micro-architecture specifications from requirements.
• Deliver RTL, verification plans, and participate in debug phase.
• Conduct silicon power measurements and power correlation.
• Lead full chip debug using ARM IPs and multi-domain clocking environments.
• Collaborate with verification teams to ensure timing closure and integration.

Skills

ASIC design

Low power architecture

Power estimation

SoC debugging

silicon bring-up

Power intent/implementation

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

ARM IP based full chip debugging

AMBA (AHB/APB/AXI)

PCIe/USB peripherals

Multi-domain clocking

Job description

Qualcomm Atheros, Inc. in Santa Clara, CA is seeking a Design Engineer (Low Power) to drive low power ASIC design from specification through silicon bring-up. The role emphasizes ARM IP-based full chip debugging, power intent, and multi-domain clocking within a fast-paced wireless technology team.

You will develop architectural specifications, own the power design flow, perform power measurements, and collaborate with verification to achieve timing closure and robust silicon deployment.