Lead SoC Packaging Architect for Next-Gen Chips

W3Global; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Commuter benefits

401(k)

Job summary

The Client is seeking a Principal Packaging Engineer to lead package architecture and development for next-generation SoC products in Santa Clara, CA. You will oversee semiconductor packaging from concept through production, collaborating with silicon, board, thermal, and manufacturing teams.

The ideal candidate has deep expertise in advanced packaging, SI/PI, substrates, and cross-functional optimization to deliver high-performance, manufacturable solutions for cutting-edge semiconductor

Qualifications

• Extensive experience developing advanced semiconductor packages for high-performance SoCs.
• Strong knowledge of package architecture, substrate technologies, bumping, assembly processes, and semiconductor manufacturing.
• Experience co-optimizing package designs with silicon, board, signal integrity, power integrity, thermal, and mechanical engineering teams.
• Hands-on experience with signal integrity, power integrity, thermal management, and reliability considerations in advanced packages.
• Ability to balance performance, cost, yield, manufacturability, and development schedules.
• Excellent communication, collaboration, and technical problem-solving skills.

Responsibilities

• Own semiconductor package architecture from concept through production for advanced SoC products.
• Collaborate with silicon and architecture teams to optimize package, die, board, and system designs for performance, power, cost, and manufacturability.
• Drive package technology selection, including flip-chip, advanced substrates, fan-out packaging, and multi-die integration.
• Lead package design, bump planning, substrate definition, escape routing, and assembly coordination with OSAT and substrate vendors.
• Manage package-level signal integrity and power integrity planning for high-speed interfaces, including LPDDR, PCIe, Ethernet, and other high-speed I/O.
• Collaborate with thermal, mechanical, reliability, design-for-manufacturing (DFM), and qualification teams.
• Coordinate with foundries, assembly partners, substrate suppliers, and test partners to deliver products successfully into production.
• Define and contribute to the long-term semiconductor packaging technology roadmap.

Skills

Semiconductor packaging

Signal integrity

Power integrity

Substrate technologies

Package architecture

Cross-functional collaboration

High-speed I/O

Job description

The Client is seeking a Principal Packaging Engineer to lead package architecture and development for next-generation SoC products in Santa Clara, CA. You will oversee semiconductor packaging from concept through production, collaborating with silicon, board, thermal, and manufacturing teams.

The ideal candidate has deep expertise in advanced packaging, SI/PI, substrates, and cross-functional optimization to deliver high-performance, manufacturable solutions for cutting-edge semiconductor