Packaging Engineering Director: High-Speed Interconnects

SiMa.ai; San Jose (CA); On-site; USD 231,000 - 358,000; Full time

Job summary

SiMa.ai is seeking a Technical Director of Packaging Engineering in San Jose, CA to drive high‑performance FCBGA and SiP packaging from definition to mass production. This hands‑on leadership role requires owning SI/PI for LPDDR5x/6, PCIe Gen5, and related interfaces, while coordinating OSAT and substrate suppliers and leading a small, high‑impact team.

You will work closely with Design, Hardware and QA teams, ensuring robust thermo‑mechanical, reliability, and cost constraints are met, with

Qualifications

• BS/MS in Electrical/Mechanical/Materials or related field with 10+ years in FCBGA/SiP packaging.
• Hands-on SI/PI design and simulation of high-speed DRAM (LPDDR5x/6), PCIe Gen5, UCIe with lab correlation.
• Package substrate design: bump/ball map, stack-up, routing, and design-rule trade-offs with vendors.
• SiP: multi‑die and SoC-plus-memory integration; automotive qualification (AEC‑Q100, PPAP).

Responsibilities

• Own package SI/PI hands‑on for high‑speed interfaces and lab correlation.
• Lead packaging development from architecture to mass production and qualification.
• Drive OSAT and substrate supplier relationships: selection, qualification, and cost roadmaps.
• Packaging NPI activities including characterization, qualification and productization.
• Travel up to 10%.

Skills

SI/PI design

High-speed interfaces

LPDDR5x/6

PCIe Gen5

UCIe channels

Lab correlation

HFSS/SIwave

Cadence Sigrity/Clarity

Keysight ADS

Electrical/Mechanical packaging

Education

BS/MS in Electrical Engineering, Mechanical Engineering, Materials Science or related

Tools

Ansys HFSS/SIwave

Cadence APD+/SiP Layout

Job description

SiMa.ai is seeking a Technical Director of Packaging Engineering in San Jose, CA to drive high‑performance FCBGA and SiP packaging from definition to mass production. This hands‑on leadership role requires owning SI/PI for LPDDR5x/6, PCIe Gen5, and related interfaces, while coordinating OSAT and substrate suppliers and leading a small, high‑impact team.

You will work closely with Design, Hardware and QA teams, ensuring robust thermo‑mechanical, reliability, and cost constraints are met, with