Principal Packaging Engineer

W3Global; Santa Clara (CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Medical insurance

Dental insurance

Vision insurance

Commuter benefits

401(k)

Résumé du poste

The Client is seeking a Principal Packaging Engineer to lead package architecture and development for next-generation SoC products in Santa Clara, CA. You will oversee semiconductor packaging from concept through production, collaborating with silicon, board, thermal, and manufacturing teams.

The ideal candidate has deep expertise in advanced packaging, SI/PI, substrates, and cross-functional optimization to deliver high-performance, manufacturable solutions for cutting-edge semiconductor

Qualifications

• Extensive experience developing advanced semiconductor packages for high-performance SoCs.
• Strong knowledge of package architecture, substrate technologies, bumping, assembly processes, and semiconductor manufacturing.
• Experience co-optimizing package designs with silicon, board, signal integrity, power integrity, thermal, and mechanical engineering teams.
• Hands-on experience with signal integrity, power integrity, thermal management, and reliability considerations in advanced packages.
• Ability to balance performance, cost, yield, manufacturability, and development schedules.
• Excellent communication, collaboration, and technical problem-solving skills.

Responsabilités

• Own semiconductor package architecture from concept through production for advanced SoC products.
• Collaborate with silicon and architecture teams to optimize package, die, board, and system designs for performance, power, cost, and manufacturability.
• Drive package technology selection, including flip-chip, advanced substrates, fan-out packaging, and multi-die integration.
• Lead package design, bump planning, substrate definition, escape routing, and assembly coordination with OSAT and substrate vendors.
• Manage package-level signal integrity and power integrity planning for high-speed interfaces, including LPDDR, PCIe, Ethernet, and other high-speed I/O.
• Collaborate with thermal, mechanical, reliability, design-for-manufacturing (DFM), and qualification teams.
• Coordinate with foundries, assembly partners, substrate suppliers, and test partners to deliver products successfully into production.
• Define and contribute to the long-term semiconductor packaging technology roadmap.

Connaissances

Semiconductor packaging

Signal integrity

Power integrity

Substrate technologies

Package architecture

Cross-functional collaboration

High-speed I/O

Description du poste

About THE Client

The Client is developing next-generation computing technology for cloud, edge computing, and Physical AI applications. Its technology supports advanced applications such as robotics, autonomous systems, drones, and other intelligent machines.

Location: Santa Clara, CA
Job Type: Full-time

About THE Client

The Client is developing next-generation computing technology for cloud, edge computing, and Physical AI applications. Its technology supports advanced applications such as robotics, autonomous systems, drones, and other intelligent machines.

This is an opportunity to contribute to the development of advanced semiconductor technology while collaborating with experienced leaders and engineers across silicon, computing, semiconductor, and AI platforms.

About The Role

The Client is seeking a Principal Packaging Engineer to lead package architecture and development for next-generation System-on-Chip (SoC) products. This role will oversee semiconductor packaging from initial concept through production, collaborating with silicon, board, system, thermal, mechanical, and manufacturing teams.

The ideal candidate will have deep expertise in advanced semiconductor packaging, package-level signal integrity (SI), power integrity (PI), substrate and assembly technologies, and cross-functional system optimization.

Key Responsibilities

• Own semiconductor package architecture from concept through production for advanced SoC products.


• Collaborate with silicon and architecture teams to optimize package, die, board, and system designs for performance, power, cost, and manufacturability.


• Drive package technology selection, including flip-chip, advanced substrates, fan-out packaging, and multi-die integration.


• Lead package design, bump planning, substrate definition, escape routing, and assembly coordination with OSAT and substrate vendors.


• Manage package-level signal integrity and power integrity planning for high-speed interfaces, including LPDDR, PCIe, Ethernet, and other high-speed I/O.


• Collaborate with thermal, mechanical, reliability, design-for-manufacturing (DFM), and qualification teams.


• Coordinate with foundries, assembly partners, substrate suppliers, and test partners to deliver products successfully into production.


• Define and contribute to the long-term semiconductor packaging technology roadmap.

Qualifications

• Extensive experience developing advanced semiconductor packages for high-performance SoCs.


• Strong knowledge of package architecture, substrate technologies, bumping, assembly processes, and semiconductor manufacturing.


• Experience co-optimizing package designs with silicon, board, signal integrity, power integrity, thermal, and mechanical engineering teams.


• Hands-on experience with signal integrity, power integrity, thermal management, and reliability considerations in advanced packages.


• Ability to balance performance, cost, yield, manufacturability, and development schedules.


• Excellent communication, collaboration, and technical problem-solving skills.

Preferred Qualifications

• Experience with chiplets, 2.5D integration, silicon bridges, or heterogeneous integration.


• Experience with High Bandwidth Memory (HBM) integration and high-bandwidth memory package architecture.


• Familiarity with advanced semiconductor process nodes, including N3, N2, or beyond.


• Experience collaborating with leading semiconductor foundries, OSAT providers, and substrate vendors.


• Experience working in a startup or early-stage semiconductor company.

Benefits

• Medical insurance


• Dental insurance


• Vision insurance


• Commuter benefits


• 401(k)