Lead SI/PI Architect for High-Speed SoCs

GlobalFoundries Engineering Private Limited; Richardson (TX); On-site; USD 153,000 - 296,000; Full time

Job summary

GlobalFoundries is seeking a highly experienced Principal Engineer, Signal Integrity & Power Integrity Leader to drive SI/PI across die, package and board for advanced silicon products, including automotive, AI, and networking applications.

You will define electrical architecture, lead SI/PI sign-off, mentor teams, and collaborate with SoC, Package, Board Design, and OSAT partners to ensure robust performance and first-pass silicon success.

Qualifications

• Master's degree or higher in Electrical Engineering, Computer Engineering, Applied Physics, Electromagnetics, or a related field.
• Minimum 10+ years of semiconductor experience in Signal Integrity, Power Integrity, Electrical Design, Package Design, System Design, or Die-Package-Board Co-Design.
• Minimum 5+ years of demonstrated experience leading SI/PI activities for complex SoCs, ASICs, high-speed interfaces, high-performance computing platforms, or heterogeneous systems.
• Strong understanding of high-speed electrical interfaces and system architectures including PCIe, Ethernet, DDR/LPDDR, SerDes, UCIe, USB, MIPI, networking, AI, and automotive platforms.
• Working knowledge and understanding of industry-standard EDA tools for package and board level simulations such as Cadence Sigrity, Cadence Clarity, Ansys HFSS, SIwave, Q3D, Synopsys tools, and related SI/PI analysis environments.
• Understanding of package and board design environments is highly desirable.
• Strong understanding of package technologies including Flip-Chip, FCBGA, WLCSP, wire-bond, advanced packaging technologies, interposers, chiplets, 2.5D, and 3D integration, along with manufacturing flows, yield considerations, and reliability standards especially related to Automotive applications.
• Excellent communication and documentation skills capable of producing clear, comprehensive requirements, architecture specifications, design methodologies, validation plans, and customer-facing technical documentation for both internal and external stakeholders.
• Collaborative mindset comfortable working in global, cross-disciplinary teams and engaging directly with customers, partners, OSATs, foundries, and ecosystem suppliers.

Responsibilities

• Lead SI/PI strategy for custom silicon products covering industrial, automotive, AI, networking, and other end-equipment applications.
• Drive the overall signal integrity and power integrity engagement on these products and establish methodologies, design guidelines, and signoff criteria to ensure robust system performance and first-pass silicon success.
• Define electrical architecture and system-level requirements in alignment with product performance, power, cost, reliability, and manufacturability goals.
• Drive architecture definition for package power delivery networks, high-speed interfaces, board topologies, and channel implementations while serving as the technical authority for electrical design decisions.
• Drive die-package-board co-design and related engineering work on interface placement, IO planning, bump assignment, floorplan optimization, package routing, board stackup definition, and power delivery implementation to achieve optimal electrical performance across the complete system.
• Cross-collaboration and system-level leadership working closely with SoC Design, Package Design, Board/System Design, Validation, and customers to develop compelling and differentiated solutions.
• Strong understanding of electrical performance challenges, package and board level tradeoffs, compliance requirements, and a proven track record in driving technology and vendor engagements.
• Drive system-level analysis performing and guiding signal integrity (SI), power integrity (PI), electromagnetic (EM), channel compliance, and electrical performance simulations across die, package, and board environments.
• Drive signoff methodologies and design closure processes across multiple engineering disciplines.
• Validation and characterization leadership with the ability to define validation strategies and characterization requirements for new products.
• Support compliance testing, simulation-to-silicon correlation, silicon bring-up, and electrical root-cause analysis while driving resolution of product performance issues.
• Mentorship and leadership in providing technical guidance and mentorship to engineers across the hardware engineering organization.
• Lead technical initiatives, establish engineering best practices, align team direction with business and product priorities, and serve as the technical SME for SI/PI and electrical co-design methodologies.
• Customer and vendor engagement leadership to drive technical alignment, discussions, and execution with customers, package vendors, PCB vendors, OSAT partners, and ecosystem suppliers.
• Drive customer discussions and align both internal product and technology roadmaps while supporting electrical architecture and system-level performance requirements.
• Stay current with the latest trends in signal integrity, power integrity, advanced packaging, chiplets, UCIe, power delivery architectures, AI/HPC platforms, and next-generation high-speed interconnect technologies.
• Drive design innovation, provide technical leadership and mentoring within the hardware engineering team, and participate in internal and external technical forums.

Skills

Signal Integrity Leadership

Power Integrity expertise

Electromagnetic simulations

Cross-functional collaboration

Technical mentorship

Education

Master's degree or higher in Electrical Engineering

Tools

Cadence Sigrity

Cadence Clarity

Ansys HFSS

SIwave

Q3D

Synopsys tools

Job description

GlobalFoundries is seeking a highly experienced Principal Engineer, Signal Integrity & Power Integrity Leader to drive SI/PI across die, package and board for advanced silicon products, including automotive, AI, and networking applications.

You will define electrical architecture, lead SI/PI sign-off, mentor teams, and collaborate with SoC, Package, Board Design, and OSAT partners to ensure robust performance and first-pass silicon success.