Lead SerDes Validation Engineer (112G/224G PAM4)

Delos Data Inc; United States; Hybrid; USD 180,000 - 260,000; Full time

Job summary

Delos Data Inc. is seeking a SerDes Validation Lead to own physical-layer implementation, tuning, and post-silicon validation of ultra-high-speed data links (112G/224G PAM4). You will work with SI/PI, hardware, and firmware teams to correlate lab results with models and drive bring-up across systems.

The role requires hands-on experience with high-speed SerDes, tight eye margins, and lab automation using Python; US/Canada hybrid work environment with competitive compensation.

Qualifications

• Hands-on experience bringing up and validating high-speed PAM4 links (56G/112G/224G) or PCIe Gen5/Gen6.
• Deep understanding of SerDes implementation, configuration, and physical-layer debugging.
• Experience tuning TX/RX equalization to optimize eye margin and BER.
• Proficiency with high-speed lab equipment (oscilloscopes, BERTs, pattern generators, analyzers).
• Experience with script-based testing, preferably Python, for lab workflows.

Responsibilities

• Drive implementation and register-level configuration of high-speed SerDes IP blocks.
• Own transceiver equalization tuning to maximize eye margin and minimize BER.
• Lead post-silicon physical-layer bring-up and debugging of PAM4 links.
• Validate link performance using high-bandwidth test equipment.
• Collaborate with SI/PI, hardware, firmware teams to correlate lab results with models.
• Support real-time link monitoring and automated validation flows with firmware teams.
• Develop and run Python-based test and characterization workflows.
• Define best practices for SerDes bring-up, tuning, and validation across platforms.

Skills

PAM4 112G/224G

SerDes bring-up

PCIe Gen5/Gen6

Eye margin / BER

Python lab automation

High-speed measurement

Tools

Oscilloscopes

BERTs

Pattern generators

Protocol analyzers

Job description

Delos Data Inc. is seeking a SerDes Validation Lead to own physical-layer implementation, tuning, and post-silicon validation of ultra-high-speed data links (112G/224G PAM4). You will work with SI/PI, hardware, and firmware teams to correlate lab results with models and drive bring-up across systems.

The role requires hands-on experience with high-speed SerDes, tight eye margins, and lab automation using Python; US/Canada hybrid work environment with competitive compensation.