Senior SerDes Software Engineer - 224G PAM4 & UCIe

Eridu; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Eridu, a Silicon Valley hardware startup, seeks a senior SerDes software engineer to lead development, bring‑up, validation, and optimization of high‑speed interfaces. You will work on 224 Gb/s per lane Ethernet SerDes, PCIe, and UCIe interconnects with engineers across firmware, ASIC, and system software teams.

The role requires deep SerDes knowledge, robust C/C++, and Python skills, with a focus on bring‑up, diagnostics, and performance optimization in a fast‑paced environment.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science.
• Typically 10+ years of SerDes firmware or high‑speed interface validation experience.
• Strong embedded programming in C/C++ and Python for automation.

Responsibilities

• Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high‑speed SerDes PHYs.
• Lead bring‑up and optimization of 224G PAM4 SerDes in Ethernet switch, networking, and accelerator products.
• Develop software support for PCIe SerDes, including link initialization, training, equalization, and diagnostics.
• Support UCIe die‑to‑die interfaces, including PHY initialization, link training, and health monitoring.
• Create automated characterization and production‑test software for PRBS, BER, eye scans, and jitter analysis.
• Mentor engineers and serve as the organization’s technical authority for SerDes software.

Skills

C/C++

Python scripting

Firmware bring-up

SerDes knowledge

Embedded debugging

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

MDIO

I2C

SPI

PCIe configuration space

Memory‑mapped registers

Job description

Eridu, a Silicon Valley hardware startup, seeks a senior SerDes software engineer to lead development, bring‑up, validation, and optimization of high‑speed interfaces. You will work on 224 Gb/s per lane Ethernet SerDes, PCIe, and UCIe interconnects with engineers across firmware, ASIC, and system software teams.

The role requires deep SerDes knowledge, robust C/C++, and Python skills, with a focus on bring‑up, diagnostics, and performance optimization in a fast‑paced environment.