ASIC RTL/SoC Design Engineer

TetraMem - Accelerate The World; San Jose (CA); Sur place; USD 110 000 - 300 000; Plein temps

Résumé du poste

TetraMem in San Jose, CA is seeking a senior RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs.

You will integrate IP blocks, perform PPA analysis, collaborate with backend, and drive tapeout readiness while developing reusable IPs for AI and in-memory computing.

The role includes mentoring junior engineers, contributing to design reviews, and staying current with RTL methodologies to improve product quality.

Qualifications

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design.
• Experience with Verilog and SystemVerilog.
• Experience with pre-layout and post-layout simulation.
• Familiarity with AMBA APB/AXI protocol.
• Familiarity with RISC/Arm or other core architectures.
• Ability to lead architecture and provide technical leadership.
• Startup environment experience preferred.

Responsabilités

• Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
• Integrate and validate IP blocks within the larger system for seamless functionality.
• Conduct PPA analysis to optimize design trade-offs.
• Collaborate with backend team on RTL coding, implementation, and synthesis for successful tapeout.
• Develop and maintain reusable internal IPs for AI and/or in-memory computing.
• Provide support for Post-Si testing and validation, diagnosing issues to ensure product quality.
• Mentor junior engineers and share best practices to foster growth.
• Contribute to design reviews and cross-functional discussions to enhance performance and reliability.
• Stay current with RTL design trends and innovative techniques to improve quality.
• Collaborate with software, architecture, and verification teams for cohesive development.

Connaissances

RTL design

Verilog/SystemVerilog

VCS/Verdi

Pre/post-layout sim

AMBA AXI/APB

Arm/RISC cores

Technical leadership

Cross-functional teamwork

Mentoring

Formation

MS or PhD in Electrical Engineering

Outils

VCS

Verdi

Synthesis tools

Description du poste

Responsibilities

• Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs
• Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility
• Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
• Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout
• Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications
• Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product
• Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth
• Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability
• Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency
• Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery

Responsibilities

• Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs
• Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility
• Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
• Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout
• Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications
• Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product
• Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth
• Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability
• Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency
• Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery

Requirements

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
• Experience with Verilog and system Verilog
• Experience with VCS, Verdi or other industry standard tools
• Experience with pre-layout simulation and post-layout simulation
• Understanding of the design flow. Ability to work with the backend team
• Familiarity with AMBA APB AXI Protocol
• Familiarity with RISC/Arm or other core architectures
• Ability to create innovative architecture and solutions to customer requirements
• Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

• FPGA/ASIC design of image processing systems
• Working knowledge of SoC architecture such as CPU, GPU or accelerators
• Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Salary Range:

$110,000 - $300,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.

TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.