Lead RTL Design Engineer for High-Performance Chips

Cerebras; Sunnyvale (CA); Hybrid; USD 175,000 - 275,000; Full time

Job summary

A cutting-edge technology company in California is seeking a Lead Front-End Design Engineer to drive chip design and manage external ASIC vendors. The ideal candidate will have over 10 years of experience in high-performance RTL design, with a Master's degree in Computer Science or Electrical Engineering. You'll collaborate across multiple teams to address challenges in semiconductor architecture with a focus on high-performance solutions. The role offers a hybrid work environment with a competitive salary of $175,000 to $275,000.

Qualifications

• 10+ years of experience in high-performance RTL designs.
• Experience with Front End Chip integration and third-party IP.
• Proven track record of multiple silicon successes.

Responsibilities

• Drive all aspects of chip design including functional specification and RTL development.
• Manage external ASIC vendor through the product development cycle.
• Work with design verification and DFT teams for optimal test coverage.

Skills

RTL design expertise

Software and system collaboration

High-performance design

Networking stack experience

Vendor management experience

Education

Master’s degree in Computer Science or Electrical Engineering

Tools

Python

TCL

Job description

A cutting-edge technology company in California is seeking a Lead Front-End Design Engineer to drive chip design and manage external ASIC vendors. The ideal candidate will have over 10 years of experience in high-performance RTL design, with a Master's degree in Computer Science or Electrical Engineering. You'll collaborate across multiple teams to address challenges in semiconductor architecture with a focus on high-performance solutions. The role offers a hybrid work environment with a competitive salary of $175,000 to $275,000.