Lead RTL Design Engineer — Hybrid High-Performance ASICs

Cerebras Systems; Sunnyvale (CA); Hybrid; USD 175,000 - 275,000; Full time

Benefits offered by this job

Job stability with startup vitality

Opportunity to work on cutting-edge AI research

Open-source research publication

Job summary

A leading AI hardware company in Sunnyvale, California is looking for a lead front-end design engineer. In this role, you will focus on chip design and collaboration with various teams to innovate semiconductor architectures. Ideal candidates will have over 10 years of experience in RTL design and a master's degree in computer science or electrical engineering. The company offers a competitive salary range of $175,000 to $275,000 annually along with a modern work culture.

Qualifications

• 10+ years of experience in delivering complex, high performance RTL designs.
• Experience collaborating and managing external vendors.
• Knowledge of PCIe, CPU interfaces and Serdes technology.

Responsibilities

• Drive all aspects of chip design including RTL development.
• Manage external ASIC vendor through product development cycle.
• Collaborate with teams to deliver optimal performance and feature set.

Skills

RTL design

Front End Chip integration

Networking

High-performance computing

Machine learning

Python

TCL

Education

Master’s degree in Computer Science or Electrical Engineering

Tools

FPGA development toolchain

Job description

A leading AI hardware company in Sunnyvale, California is looking for a lead front-end design engineer. In this role, you will focus on chip design and collaboration with various teams to innovate semiconductor architectures. Ideal candidates will have over 10 years of experience in RTL design and a master's degree in computer science or electrical engineering. The company offers a competitive salary range of $175,000 to $275,000 annually along with a modern work culture.