Senior RTL & Microarchitecture Engineer for SoC Performance

Bolt Graphics; Sunnyvale (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

100% covered Medical, Dental, & Vision premiums

Equity - Stock Options

401(k) match

Job summary

A semiconductor startup in Sunnyvale, CA is seeking an RTL Design/Microarchitecture Engineer to define and implement key components of their graphics processors. Responsibilities include developing microarchitecture specifications, designing RTL for digital blocks, and optimizing performance and power efficiency. Ideal candidates have 5-10 years in RTL design, a degree in Electrical Engineering, and experience with tools like Synopsys VCS. The role offers a competitive salary range of $160,000–$220,000 annually and benefits including 100% covered health insurance and stock options.

Qualifications

• 5–10 years of experience in RTL design and microarchitecture.
• Strong understanding of FSMs, pipelines, caches, and memory interfaces.
• Experience working in ASIC/SoC development environments.

Responsibilities

• Define and develop microarchitecture specifications.
• Design RTL for complex digital blocks.
• Drive performance, power, and area optimizations at the microarchitecture level.
• Collaborate with verification teams for coverage and design correctness.
• Support IP integration into SoC-level environments.
• Debug issues during simulation and silicon bring-up.
• Participate in design reviews and cross-functional planning.
• Contribute to design documentation and methodology improvements.

Skills

Performance optimization techniques

Pipelining techniques

Digital design fundamentals

ASIC/SoC development

Education

Bachelor’s/Master’s degree in Electrical Engineering or related field

Tools

Synopsys VCS

Cadence Xcelium

Synopsys Design Compiler

Job description

A semiconductor startup in Sunnyvale, CA is seeking an RTL Design/Microarchitecture Engineer to define and implement key components of their graphics processors. Responsibilities include developing microarchitecture specifications, designing RTL for digital blocks, and optimizing performance and power efficiency. Ideal candidates have 5-10 years in RTL design, a degree in Electrical Engineering, and experience with tools like Synopsys VCS. The role offers a competitive salary range of $160,000–$220,000 annually and benefits including 100% covered health insurance and stock options.