Lead RISC-V SoC Post-Silicon Validation Engineer

Tenstorrent; Austin (CA); Hybrid; USD 180,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V-based SoCs. The role sits at the intersection of silicon, firmware, and system software, with heavy hands-on lab work and close collaboration across RTL, firmware, and software teams.

The position is hybrid, based out of Austin, TX, or Santa Clara, CA. We welcome candidates at various experience levels; offers align with level determined during interviews.

Qualifications

• 5+ years of experience in SoC bring-up, validation and silicon debug.
• Strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems.
• Experience debugging complex hardware/software interaction issues using lab tools and low-level software.

Responsibilities

• Lead first-silicon bring-up of RISC-V CPU-based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces.
• Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation.
• Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.

Skills

SoC bring-up

CPU architectures

RISC-V privilege modes

lab tools

cross-functional collaboration

Tools

Linux

Job description

Tenstorrent is seeking a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V-based SoCs. The role sits at the intersection of silicon, firmware, and system software, with heavy hands-on lab work and close collaboration across RTL, firmware, and software teams.

The position is hybrid, based out of Austin, TX, or Santa Clara, CA. We welcome candidates at various experience levels; offers align with level determined during interviews.