Post-Silicon RISC-V SoC Validation Engineer

Tenstorrent; Town of Texas (WI); Hybrid; USD 100.000 - 500.000; Vollzeit

Zusammenfassung

Tenstorrent is seeking a Post‑Silicon Validation Engineer to drive bring‑up, validation, and debug of RISC‑V–based SoCs across silicon, firmware, and system software. This role requires hands‑on lab experience and understanding of SoC architectures.

This hybrid role is based out of Austin, TX or Santa Clara, CA, with offers aligned to experience level. Compensation ranges from $100k to $500k, reflecting base and variable components, and Tenstorrent is an equal opportunity employer.

Qualifikationen

• 5+ years of experience in SoC bring-up, validation and silicon debug.
• Strong grasp of CPU/SoC architectures including RISC-V privilege modes, caches, coherency and memory systems.
• Able to debug hardware/software interactions using lab tools and low-level software.
• Thrives in cross-functional environments with RTL, firmware and software teams.

Aufgaben

• Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals and high-speed interfaces.
• Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation.
• Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.

Kenntnisse

SoC bring-up

RISC-V knowledge

Hardware debugging

Cross-functional collab

Jobbeschreibung

Tenstorrent is seeking a Post‑Silicon Validation Engineer to drive bring‑up, validation, and debug of RISC‑V–based SoCs across silicon, firmware, and system software. This role requires hands‑on lab experience and understanding of SoC architectures.

This hybrid role is based out of Austin, TX or Santa Clara, CA, with offers aligned to experience level. Compensation ranges from $100k to $500k, reflecting base and variable components, and Tenstorrent is an equal opportunity employer.