Lead RISC-V SoC Post-Silicon Validation

Tenstorrent; Austin, Santa Clara (TX, CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. The role sits at the intersection of silicon, firmware, and system software, with hands-on lab work and cross-functional collaboration across RTL, firmware, and software teams.

This hybrid position is based out of Austin, TX, or Santa Clara, CA, with opportunities at various experience levels.

Qualifications

• 5+ years of experience in SoC bring-up, validation, and silicon debug.
• Strong knowledge of CPU/SoC architectures, including RISC-V privilege modes, caches, memory systems.

Responsibilities

• Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces.
• Develop and debug bare-metal tests and boot flows; contribute to Linux bring-up and driver validation.
• Provide actionable feedback and drive fixes for future silicon revisions.

Skills

RISC-V

SoC bring-up

Silicon debug

Cross-functional

Lab tools

Tools

JTAG

Oscilloscopes

Logic analyzers

Linux

Job description

Tenstorrent is seeking a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. The role sits at the intersection of silicon, firmware, and system software, with hands-on lab work and cross-functional collaboration across RTL, firmware, and software teams.

This hybrid position is based out of Austin, TX, or Santa Clara, CA, with opportunities at various experience levels.