Lead Physical Design Engineer – Tapeouts & AI Silicon

Architect

Palo Alto (CA)

On-site

USD 180,000 - 320,000

Full time

9 days ago

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Job summary

Architect Labs in Palo Alto is seeking its first Physical Design engineer to build the PD function from the ground up and deliver tapeout-ready flows for 3nm/2nm nodes and beyond. You will own the methodology and hands-on execution for physical implementation, from spec-to-netlist to GDS delivery.

You will drive floorplanning, placement, routing, clocking, and signoff, while collaborating with AI researchers and foundries to push PPA targets.

Qualifications

Tapeout ownership: Multiple production tapeouts with signoff responsibility at 3nm/2nm.
Build production PD methodology from scratch for advanced nodes including PDK/library qualification.
Deep expertise in hierarchical implementation, timing, variation, and power integrity.
Hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus with timing and extraction tools.
Automation: Tcl and Python scripts for maintainable flows and PPA reporting.
Ability to lead flow establishment, debug closure problems, and explain trade-offs.

Responsibilities

Build the methodology: netlist-to-GDS flow, PDKs, libraries, constraints, automation.
Own implementation: floorplanning, power planning, placement, clocking, routing, ECOs.
Drive signoff: timing, SI, EM/IR, DRC/LVS, and foundry checks to GDS delivery.
Work with AI researchers to feed post-route results back into architecture and RTL.
Lead technical partnerships with foundries, EDA vendors, and IP providers.
Build the team: set PD standards, roadmap, and hiring priorities, while remaining hands-on.