Lead Physical Design Engineer – SoC & Photonics

Neurophos, Inc.; Town of Texas, Northern (WI, KY); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

100% health plan premiums for you and/

Unlimited PTO

401(k) matching and stock options

Voluntary benefits: Dental, Vision, L

Personalized Benefits

Job summary

Neurophos, Inc. is hiring a permanent Physical Design / Implementation Lead for the digital design team in the United States. This on-site role will manage RTL to tapeout across multiple nodes, including coordinating a multi-site team at Austin, TX or San Jose, CA.

You will lead the digital implementation flow, drive timing closure and IP ownership, and partner with RTL/DV, analog, and other leads to deliver optimized GDSII implementations at scale.

Qualifications

• Track record leading physical design / implementation on large, complex SoCs through tapeout.
• Hands-on experience on advanced nodes; 7nm–3nm FinFET class experience required.
• Deep power and clock design experience at scale.
• Experience leading and growing a team.

Responsibilities

• Own physical design and implementation end-to-end, from synthesis through tapeout, on leading-edge process nodes (TSMC N3 strongly preferred; deep FinFET-class experience, 7nm–3nm, required).
• Optimize and automate our synthesis flow, and lead the intake of new process technology as we bring on new nodes.
• Optimize and automate the timing closure process at the block and subsystem level
• Design and optimization of power and clock architecture distribution networks.
• Own the integration of analog/mixed-signal components into the digital implementation flow, building the process and working relationship between analog and digital teams.
• Own physical verification and IP/library management for the digital design org.
• Build and lead a physical design team: hire, ramp, and manage the engineers under you as the group scales.
• Work closely with the RTL/DV, Analog and other team leads on cross-functional flow and schedule decisions.

Skills

Physical design leadership

SoC implementation

Power/clock design at scale

Team leadership

Advanced node experience

Tools

Cadence toolchain

Job description

Neurophos, Inc. is hiring a permanent Physical Design / Implementation Lead for the digital design team in the United States. This on-site role will manage RTL to tapeout across multiple nodes, including coordinating a multi-site team at Austin, TX or San Jose, CA.

You will lead the digital implementation flow, drive timing closure and IP ownership, and partner with RTL/DV, analog, and other leads to deliver optimized GDSII implementations at scale.