Senior SoC Architect - Photonics AI Compute

Neurophos; Austin, Sunnyvale (TX, CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

100% coverage of base health plan for你

Unlimited PTO

401(k) matching and stock options

Voluntary benefits package

Job summary

Neurophos is seeking a SoC Lead to own integration of the full chip or major module for a high-bandwidth, low-power AI hardware system. You will define and defend approaches across DFT, power, timing, and interconnect while collaborating with system architects, RTL, physical design, and verification leads.

You will also help scale the design organization by hiring and mentoring specialists. You will lead architecture discussions at the chip level, work hands-on when needed, and help drive

Qualifications

• Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.
• Breadth across domains: closed timing on a block and argued interconnect architecture in the same design cycle.
• Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design.
• Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.

Responsibilities

• Lead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows.
• Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
• Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
• Go deep on any domain when needed, staying hands-on with the flow at every level.
• Help scale the design org: hire, mentor, and grow engineers across specialty domains (subsystem roles are open now and will continue to open).
• Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs.

Skills

Technical leadership

Full-chip tapeouts

CPU design

Interconnect / data-fabric design

Advanced process nodes

Cadence toolchain

Tools

Cadence

Job description

Neurophos is seeking a SoC Lead to own integration of the full chip or major module for a high-bandwidth, low-power AI hardware system. You will define and defend approaches across DFT, power, timing, and interconnect while collaborating with system architects, RTL, physical design, and verification leads.

You will also help scale the design organization by hiring and mentoring specialists. You will lead architecture discussions at the chip level, work hands-on when needed, and help drive