Design Verification Lead: AI Hardware & Photonics (Onsite)

Neurophos; Austin (TX); On-site; USD 190,000 - 260,000; Full time

Benefits offered by this job

Health premium coverage

HSA contributions

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits package

Job summary

Neurophos, located in Austin, TX (onsite) with a niche in silicon photonics, seeks a seasoned Verification Architect to lead end‑to‑end verification of GPU-class/ASIC blocks. You will own testbench architecture, integrate VIPs, and drive emulation and tapeout readiness.

Join a fast‑growing AI hardware startup and shape the verification roadmap. You will coordinate across RTL, physical design, DFT and validation teams while leveraging AI tooling to accelerate coverage closure.

Qualifications

• 8 to 15 years in design verification, including leading verification on a GPU-class or complex compute ASIC through tapeout.
• Deep UVM and SystemVerilog expertise, including ownership of testbench architecture, formal verification, coverage analysis and CI/CD methodology.
• Gate-level simulation experience. You know what gate sim costs you in visibility and where it belongs in a tapeout schedule.
• Verification experience on a chip with many independently developed blocks and analog components, including integration of analog models.
• Comfort standing up a verification environment end to end, including emulation infrastructure.
• Breadth across the flow, from module-level simulation through SoC integration and into validation planning.

Responsibilities

• Own verification methodology and testbench architecture, built on UVM with a strong emphasis on AI driven flows.
• Build the verification plan across levels: module-level simulation, SoC integration, interface checks, top-level IO, and how each feeds the validation plan.
• Specify, evaluate and Integrate third party VIP into the environment Own gate-level simulation with SDF-annotated timing as part of tapeout closure.
• Extend our FPGA-based verification harness so modules can be exercised with real code, quickly, without burning simulator licenses.
• Stand up and operate our emulation environment, including provisioning and execution on cloud-hosted infrastructure.
• Use AI tooling to generate and iterate testbenches and assertions, optimizing based on coverage feedback, and iterating to ensure high quality verification.
• Build and lead the verification team, partnering with system architecture, RTL design, physical design, DFT and validation.

Skills

UVM / SystemVerilog

Gate-level verification

SoC verification

CI/CD

Emulation infrastructure

Team leadership

Analog model integration

Hands-on emulation

Cadence toolchain

FPGA verification

WREAL models

Tools

Palladium

Cadence toolchain

FPGA-based verification

WREAL

Job description

Neurophos, located in Austin, TX (onsite) with a niche in silicon photonics, seeks a seasoned Verification Architect to lead end‑to‑end verification of GPU-class/ASIC blocks. You will own testbench architecture, integrate VIPs, and drive emulation and tapeout readiness.

Join a fast‑growing AI hardware startup and shape the verification roadmap. You will coordinate across RTL, physical design, DFT and validation teams while leveraging AI tooling to accelerate coverage closure.