Senior Physical Design Lead for AI Photonics

Neurophos; Austin, Sunnyvale (TX, CA); On-site; USD 200,000 - 260,000; Full time

Benefits offered by this job

Health insurance

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Job summary

Neurophos is seeking a senior Physical Design Lead to own end-to-end implementation for a next-generation SoC in a high-performance AI hardware setting. You will drive the RTL-to-tapeout process and build a multi-site team across leading-edge nodes.

Based in Austin, TX or San Jose, CA, the role requires hands-on back-end leadership, strong power/clock design experience, and collaboration across RTL, DV, analog and other teams to optimize the delivery of IP and libraries.

Qualifications

• Track record leading physical design / implementation on large, complex SoCs through tapeout.
• Hands-on experience with advanced nodes (TSMC N3 preferred).
• Experience building and scaling a hardware design team.
• Strong power and clock distribution design expertise.

Responsibilities

• Own physical design and implementation end-to-end, from synthesis through tapeout, on leading-edge process nodes.
• Optimize and automate the synthesis flow and lead new node technology integration.
• Optimize timing closure at block and subsystem levels.
• Design and optimize power and clock networks.
• Coordinate analog/mixed-signal integration with digital teams.
• Manage physical verification and IP/library for the digital design org.
• Build and lead the physical design team, hiring and ramping engineers.
• Collaborate with RTL/DV and other leads on flow and schedule.

Skills

Physical design leadership

SoC implementation

Tapeout experience

Team building

Tools

Cadence toolchain

Job description

Neurophos is seeking a senior Physical Design Lead to own end-to-end implementation for a next-generation SoC in a high-performance AI hardware setting. You will drive the RTL-to-tapeout process and build a multi-site team across leading-edge nodes.

Based in Austin, TX or San Jose, CA, the role requires hands-on back-end leadership, strong power/clock design experience, and collaboration across RTL, DV, analog and other teams to optimize the delivery of IP and libraries.