Lead Physical Design Engineer: End-to-End Signoff

SiTime Corporation; Tempe, Santa Clara (AZ, CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

401k plan

Equity grants

Job summary

SiTime Corporation seeks a seasoned Principal Physical Design Engineer to own end-to-end physical implementation from synthesis to GDSII signoff. You will lead cross-functional teams, drive PPA improvements, and establish robust signoff methodologies across multiple programs.

You will apply low-power techniques, collaborate with layout/chip-top teams, and mentor engineers to meet tight schedules in a demanding environment.

Qualifications

• Hands-on ASIC physical design experience, with a clear record of driving designs from concept through successful tape-out on advanced process nodes.
• Deep hands-on experience with standard physical implementation and signoff tools, such as Cadence Innovus or Synopsys IC Compiler II/Fusion Compiler, together with STA, formal, physical-verification, and power-integrity platforms.
• Strong scripting capability in Tcl, Perl, and/or Python, applied to flow automation, constraint generation, and custom reporting.
• Strong understanding of SDC timing constraints and concurrent MMMC optimization throughout the physical design cycle (Placement, CTS, and Routing).

Responsibilities

• Serve as the technical focal point for physical design, leading implementation and signoff reviews, mentoring engineers, and establishing reusable methodologies across multiple programs.
• Lead and execute end-to-end physical design for complex digital blocks and subsystems, from synthesis through GDSII signoff, including floorplanning, power planning, place and route, clock tree synthesis, STA, ECOs, DRC, LVS, and EMIR.
• Develop and continuously improve automated physical-design and signoff flows to increase productivity and reduce risk across programs.
• Participate in architecture and design reviews, providing physical-implementation insight to avoid downstream PPA, signoff, and schedule risks.
• Architect and apply low-power implementation strategies including clock gating, power gating, and multi-voltage design.

Skills

Physical design

Tape-out leadership

Place & Route

Power integrity

Scripting Tcl/Python

Clock tree synthesis

Education

BS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys IC Compiler II

Job description

SiTime Corporation seeks a seasoned Principal Physical Design Engineer to own end-to-end physical implementation from synthesis to GDSII signoff. You will lead cross-functional teams, drive PPA improvements, and establish robust signoff methodologies across multiple programs.

You will apply low-power techniques, collaborate with layout/chip-top teams, and mentor engineers to meet tight schedules in a demanding environment.