Principal Physical Design Engineer - Lead PNR & Signoff (Equity)

SiTime Corp.; Santa Clara (CA); On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Quarterly bonus

Equity grants

401k plan

Health and wellness

Job summary

SiTime Corp. seeks a seasoned Principal Physical Design Engineer to lead physical implementation and signoff of complex digital blocks. You will own from synthesis to GDSII signoff, drive PPA and schedule outcomes, and establish best practices across programs.

As a technical leader, you will shape methodologies, resolve cross-functional challenges, and mentor teams while promoting low-power implementation and multi-voltage design across multiple tape-outs.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field with minimum 10 years of relevant experience, or Ph.D. with minimum 6 years.
• Hands-on ASIC physical design experience from concept to tape-out on advanced nodes.
• Proficiency with physical-implementation and signoff tools (STA, ECOs, DRC, LVS).
• Strong scripting in Tcl, Perl, Python for automation and reporting.

Responsibilities

• Lead implementation and signoff reviews for complex digital blocks and subsystems.
• Drive end-to-end physical design from synthesis to GDSII signoff, including P&R, clock tree, STA, and DRC/LVS checks.
• Develop automated physical-design and signoff flows to boost productivity and reduce risk.
• Contribute to architecture and design-spec reviews with early physical-design input.
• Apply low-power strategies like clock gating and multi-voltage design.
• Collaborate with chip-top layout teams to integrate digital blocks with mixed-signal designs.

Skills

ASIC physical design

Scripting Tcl/Perl/Python

STA

Place & Route

Education

BS in Electrical Engineering

PhD (optional)

Tools

Cadence Innovus

Synopsys IC Compiler II/Fusion Compiler

Job description

SiTime Corp. seeks a seasoned Principal Physical Design Engineer to lead physical implementation and signoff of complex digital blocks. You will own from synthesis to GDSII signoff, drive PPA and schedule outcomes, and establish best practices across programs.

As a technical leader, you will shape methodologies, resolve cross-functional challenges, and mentor teams while promoting low-power implementation and multi-voltage design across multiple tape-outs.