Principal Physical Design Engineer

SiTime Corporation; Tempe, Santa Clara (AZ, CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

401k plan

Equity grants

Résumé du poste

SiTime Corporation seeks a seasoned Principal Physical Design Engineer to own end-to-end physical implementation from synthesis to GDSII signoff. You will lead cross-functional teams, drive PPA improvements, and establish robust signoff methodologies across multiple programs.

You will apply low-power techniques, collaborate with layout/chip-top teams, and mentor engineers to meet tight schedules in a demanding environment.

Qualifications

• Hands-on ASIC physical design experience, with a clear record of driving designs from concept through successful tape-out on advanced process nodes.
• Deep hands-on experience with standard physical implementation and signoff tools, such as Cadence Innovus or Synopsys IC Compiler II/Fusion Compiler, together with STA, formal, physical-verification, and power-integrity platforms.
• Strong scripting capability in Tcl, Perl, and/or Python, applied to flow automation, constraint generation, and custom reporting.
• Strong understanding of SDC timing constraints and concurrent MMMC optimization throughout the physical design cycle (Placement, CTS, and Routing).

Responsabilités

• Serve as the technical focal point for physical design, leading implementation and signoff reviews, mentoring engineers, and establishing reusable methodologies across multiple programs.
• Lead and execute end-to-end physical design for complex digital blocks and subsystems, from synthesis through GDSII signoff, including floorplanning, power planning, place and route, clock tree synthesis, STA, ECOs, DRC, LVS, and EMIR.
• Develop and continuously improve automated physical-design and signoff flows to increase productivity and reduce risk across programs.
• Participate in architecture and design reviews, providing physical-implementation insight to avoid downstream PPA, signoff, and schedule risks.
• Architect and apply low-power implementation strategies including clock gating, power gating, and multi-voltage design.

Connaissances

Physical design

Tape-out leadership

Place & Route

Power integrity

Scripting Tcl/Python

Clock tree synthesis

Formation

BS in Electrical Engineering

PhD in Electrical Engineering

Outils

Cadence Innovus

Synopsys IC Compiler II

Description du poste

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary

SiTime is seeking a seasoned Principal Physical Design Engineer to lead the physical implementation and signoff of complex digital blocks and subsystems. The successful candidate will take end-to-end ownership from synthesis and floorplanning through GDSII signoff, driving power, performance, area, reliability, and schedule outcomes.This role serves as a technical leader for physical design, shaping implementation methodology and automation, resolving complex cross-functional challenges, and establishing engineering best practices across multiple programs.

We value diverse experiences, perspectives, and career paths, and welcome candidates who are excited to contribute to our mission.

Responsibilities:

• Serve as the technical focal point for physical design, leading implementation and signoff reviews, mentoring engineers, and establishing reusable methodologies across multiple programs.
• Lead and execute end-to-end physical design for complex digital blocks and subsystems, from synthesis through GDSII signoff, including floorplanning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal equivalence check, design rule checking (DRC), layout versus schematic (LVS), power, and EMIR.
• Develop and continuously improve automated, reproducible physical-design and signoff flows to increase productivity, reduce execution risk, and ensure consistent design quality across multiple programs.
• Participate actively in architecture and design-specification reviews, providing physical-implementation insight early to avoid downstream PPA, signoff, and schedule risks.
• Architect and apply low-power implementation strategies including clock gating, power gating, power‑aware implementation and multi‑voltage design to meet product‑level power budgets.
• Work closely with the chip‑top layout and integration teams to integrate digital blocks into mixed‑signal, custom‑layout top‑level designs, resolving physical, DRC, LVS, power, clock, EMIR, and connectivity issues at block boundaries.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Qualifications & Requirements:

• BS. in Electrical Engineering, Computer Engineering, or a related field with a minimum of 10 years of relevant experience, or a Ph.D. with a minimum of 6 years of relevant experience.
• Hands‑on ASIC physical design experience, with a clear record of driving designs from concept through successful tape‑out on advanced process nodes.
• Deep hands‑on experience with industry‑standard physical implementation and signoff tools, such as Cadence Innovus or Synopsys IC Compiler II/Fusion Compiler, together with STA, formal, physical‑verification, and power‑integrity platforms.
• Strong scripting capability in Tcl, Perl, and/or Python, applied to flow automation, constraint generation, and custom reporting.
• Strong understanding of SDC timing constraints and concurrent MMMC optimization throughout the physical design cycle (Placement, CTS, and Routing).
• Thorough knowledge of STA concepts, constraints and methodologies.
• Hands‑on experience setting up and executing functional and timing ECOs through industry‑standard ECO flows to signoff.
• Strong analytical and problem‑solving instincts, and the ability to communicate complex technical trade‑offs clearly to both peers and leadership.
• Drive technical alignment across cross‑functional teams by communicating implementation constraints, design trade‑offs, and execution risks, and by influencing decisions that impact PPA, signoff, and schedule.
• English proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.

Desired Characteristics & Attributes:

• 12+ years of relevant physical‑design experience, including technical leadership across multiple tape‑outs.
• Prior experience bringing up Place & Route (PnR) flow from scratch
• Proven experience implementing low‑power methodologies including clock gating, power gating, and multi‑voltage domain design.
• Experience in dynamic and static power analysis, EMIR analysis, and driving corrective actions to meet signoff targets.
• Solid understanding of semiconductor process technology, device physics, and Design for Manufacturability (DFM) principles that affect physical implementation decisions.
• Demonstrated ability to drive multiple chip implementations in parallel while maintaining schedule and signoff quality.

Compensation:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals - reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Benefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.