Lead Mixed-Signal RTL Design Engineer for AI Power

TYLsemi; San Jose (CA); Hybrid; USD 223,125 - 301,875; Full time

Job summary

TylSemi, Inc. is seeking a lead for micro-architecture and RTL design of a mixed-signal chiplet focused on intelligent power optimization for AI/HPC.

Responsibilities include translating MATLAB/Simulink controller models to production RTL, implementing digital PID/cascade loops, and collaborating with analog designers to optimize loop performance across PVT corners while aiding silicon bring-up.

Qualifications

• Strong mixed-signal background with power circuits and digital control systems.
• Proven ability to convert control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded).
• Deep knowledge of digital PID implementation: quantization, sampling, delay, fixed-point, limit cycling.

Responsibilities

• Micro-architect and own toplevel RTL for mixed-signal chip with analog circuits and digital logic.
• Architect/d implement digital PID/cascade control loops for high-frequency IVRs.
• Translate validated models into production-quality RTL (Verilog/SystemVerilog).
• Design/implement supporting digital blocks: ADC interface, DPWM.
• Collaborate with analog designers on loop compensation and sensor design.
• Analyze and optimize area, power, timing, and metastability across PVT corners.
• Support silicon bring-up, debugging, and lab hardware.

Skills

Mixed-signal background

HDL Verilog/SystemVerilog

Digital PID implementation

Digital control systems

DPWM / digital PWM modulators

Analog-digital co-simulation

Silicon bring-up / debugging

HDL Coder experience

Education

BSEE / MSEE or PhD

Tools

Synopsys VCS

Verdi

Design Compiler

PrimeTime

Cadence flows

Job description

TylSemi, Inc. is seeking a lead for micro-architecture and RTL design of a mixed-signal chiplet focused on intelligent power optimization for AI/HPC.

Responsibilities include translating MATLAB/Simulink controller models to production RTL, implementing digital PID/cascade loops, and collaborating with analog designers to optimize loop performance across PVT corners while aiding silicon bring-up.