Principal Mixed Signal RTL Design Engineer

TylSemi; San Jose (CA); On-site; USD 175,000 - 350,000; Full time

Job summary

TylSemi in San Jose is seeking a Principal Mixed Signal RTL Design Engineer to lead silicon-level RTL for intelligent power optimization in AI/HPC applications. You will translate control models to high-quality HDL, design DPWM modules, and collaborate with analog teams on loop compensation and sensor effects.

This role requires strong power-management IC experience and a track record in high-performance mixed-signal design.

Qualifications

• Strong mixed-signal background with power circuits and digital control.
• Experience converting control algorithms into synthesizable RTL (Verilog/SystemVerilog).

Responsibilities

• Lead micro-architecture and RTL design for mixed-signal chiplet.
• Architect and implement digital PID/control loops for high-frequency IVRs.
• Translate MATLAB/Simulink controller models into production RTL (Verilog/SystemVerilog).
• Design ADC interface and DPWM blocks.
• Collaborate with analog designers on compensation and sensor design.
• Optimize for area, power, timing, and metastability across PVT corners.
• Support silicon bring-up and lab hardware debugging.

Skills

Mixed-signal design

RTL design

Verilog/SystemVerilog

HDL Coder

PID control

DPWM

Co-simulation

Education

BSEE / MSEE or PhD

Tools

HDL Coder

Job description

Principal Mixed Signal RTL Design Engineer

About the role

• Lead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing.

What you'll do

• Micro-architect and own top-level RTL for Mixed-signal chip with analog circuits, micro-controller and other logic functions.
• Architect, and implement digital PID / cascade control loops (voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs.
• Develop micro-architecture and implement RTL for control of mixed-signal circuits.
• Translate validated MATLAB/Simulink controller models into production-quality RTL (Verilog / SystemVerilog) using HDL Coder or manual high-quality coding.
• Design and implement supporting digital blocks: ADC interface, DPWM (digital PWM).
• Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting.
• Analyze and optimize for area, power, timing, and metastability in the digital controller across PVT corners.
• Support silicon bring-up, debug, and controller on lab hardware.

What We're Looking For

• Strong mixed-signal background: solid understanding of power circuits and digital control systems, digital filters, etc.
• Proven experience converting control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded Verilog/SystemVerilog).
• Deep knowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed-point arithmetic, and limit cycling.
• Familiarity with high-frequency power converter control and digital PWM modulators (DPWM).
• Experience with mixed-signal verification flows (analog-digital co-simulation).
• Good understanding of analog effects impacting digital control: loop delay, sensor non-idealities, inductor non-linearities, PDN resonances.
• BSEE / MSEE or PhD with 8+ years of relevant experience in power management ICs or high-performance mixed-signal design.

Nice to Have

• Prior experience designing digital controllers for integrated voltage regulators (IVRs), point-of-load (PoL) converters, or high-current AI/HPC power delivery.
• Experience with formal verification or assertion-based mixed-signal verification.

Pay range for this role is: 175,000 - 350,000 USD per year (San Jose (HQ)).