Principal Micro-architect, Coherent Interconnect

Samsung Semiconductor; San Jose (CA); Sur place; USD 222 000 - 365 000; Plein temps

Avantages offerts par ce poste

Medical

Dental

Vision

Life insurance

401(k)

Free onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Wellness incentives

Long-term incentive plan

Relocation

Résumé du poste

Samsung Semiconductor is seeking a Principal Micro-architect to lead microarchitecture development of custom coherent interconnect IP and LLC blocks for next‑generation designs. You will drive RTL design, optimize for performance and power, and collaborate with system architects, verification, and physical design teams.

The role requires strong computer architecture background, leadership experience, and deep Verilog/SystemVerilog expertise across ASIC flows.

Qualifications

• 15+ years with a CS/CE degree or 13+ with MS or 11+ with PhD; leadership in RTL design.
• Strong RTL design experience for coherent interconnect and LLC blocks.
• Experience from architecture definition through RTL implementation.
• Familiar with mesh, ring, crossbar, and AMBA protocols (CHI/ACE/AXI).
• Deep expertise in Verilog/SystemVerilog and ASIC flows (STA, DFT, ECO).
• Memory subsystem and cache coherency knowledge; strong collaboration skills.

Responsabilités

• Own development and delivery of coherent interconnect IP and LLC blocks.
• Collaborate with system architects on next‑gen architectures.
• Define microarchitecture from exploration to detailed specs.
• Partner with verification for functional correctness and validation.
• Develop RTL that meets performance, power and area goals.
• Work with performance/power teams to optimize RTL/architecture.
• Coordinate with physical design and CAD to resolve timing issues.
• Provide technical leadership and mentorship to junior engineers.

Connaissances

RTL design

Architecture definition

Verilog/SystemVerilog

AMBA protocol knowledge

Memory subsystem architecture

Leadership/mentoring

Python/Perl scripting

Formation

Bachelor’s degree in Computer Science/Computer Engineering

PhD in a relevant field

Outils

Verilog/SystemVerilog

Scripting (Python/Perl)

Description du poste

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us!

Role And Responsibilities

As a Principal Micro-architect, you will lead the microarchitecture development of custom coherent interconnect IP and/or last-level cache (LLC) blocks for next-generation designs. In this role, you will drive key aspects of coherent interconnect RTL design, including performance and power optimization, logic debug, and timing closure. Success in this role requires a strong foundation in computer architecture, microarchitecture, and RTL design.

• Own the development and delivery of custom coherent interconnect IP and/or LLC blocks, ensuring high-quality execution and timely project completion.
• Collaborate closely with system architects to define and develop next-generation coherent interconnect and LLC architectures.
• Drive microarchitecture definition and specification, from early architectural exploration and microarchitectural research through detailed specification development and refinement.
• Partner with verification teams to ensure functional correctness and robust validation of the design.
• Develop high-quality RTL implementations that meet performance, power, and area (PPA) goals.
• Work with performance and power teams to optimize architecture and RTL implementations for efficiency and scalability.
• Collaborate with physical design and CAD teams to resolve implementation, timing, and integration challenges.
• Provide technical leadership and mentorship to junior engineers across the team.

Skills And Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD
• Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs
• Demonstrated experience spanning architecture definition through RTL implementation
• Familiarity with on-chip network topologies such as mesh, ring, and crossbar interconnects, along with working knowledge of Arm AMBA5 CHI, AMBA4 ACE, AXI, and related coherent interconnect protocols.
• Deep expertise in Verilog/SystemVerilog and solid understanding of the complete ASIC design flow including STA, DFT, ECO flows, etc.
• Strong understanding of memory subsystem architecture, coherent cache design, system caches, coherency mechanisms, and directory-based snoop filter protocols.
• Proven experience leading technical initiatives, mentoring engineers, and collaborating effectively across dynamic, geographically distributed teams with strong communication and interpersonal skills.
• Experience with a scripting language like Perl or Python is a plus

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

• medical
• dental
• vision
• life insurance
• 401(k)
• free onsite lunch
• employee purchase program
• tuition assistance (after 6 months)
• paid time off
• wellness incentives
• many more
• regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance
• role might be eligible to participate in long term incentive plan and relocation

Trade Secrets

By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

U.S. Export Control

This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

#SARC #ACL

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