Lead HPC Datacenter Package Design Architect

Qualcomm Incorporated; San Diego (CA); On-site; USD 210,000 - 315,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Principal Engineer/Director of Engineering to lead CHS Datacenter package design, driving high-performance compute packaging strategies from concept to production.

You will guide cross-functional teams across silicon, packaging, platform, and manufacturing to meet aggressive performance and cost targets. The role emphasizes leadership, deep packaging expertise, and collaboration with OSATs and foundries to advance 2.5D/3D integration, interposers, HBM,

Qualifications

• Proven leadership of advanced package engineering teams.
• Deep expertise in multi-die 2.5D/3D packaging for HPC/AI/server products.
• Strong experience with HBM, interposers, and high-density substrates.
• Ability to translate performance and cost goals into package requirements.
• Experience collaborating with foundries, OSATs, and EDA partners.

Responsibilities

• Provide technical and organizational leadership for the Datacenter package team.
• Own end-to-end advanced package architecture from concept to production.
• Drive architecture selection for 2.5D/3D integration and interposer tech.
• Lead chip-package-board co-design across floorplanning and routing.
• Collaborate with silicon design, platform, SI/PI, thermal, and manufacturing teams.

Skills

Leadership experience

2.5D/3D packaging

HBM interposers

Chip-package-board co-design

SiP integration

High-speed I/O

Design-for-manufacturability

Executive communication

Foundry collaboration

Education

Bachelor's degree in EE/CE

Master's degree in EE/ME/Materials

PhD in Engineering

Tools

Cadence APD/SiP

Siemens Xpedition

Calibre

XtractIM/PowerSI/HFSS/Q3D

Job description

Qualcomm Technologies, Inc. is seeking a Principal Engineer/Director of Engineering to lead CHS Datacenter package design, driving high-performance compute packaging strategies from concept to production.

You will guide cross-functional teams across silicon, packaging, platform, and manufacturing to meet aggressive performance and cost targets. The role emphasizes leadership, deep packaging expertise, and collaboration with OSATs and foundries to advance 2.5D/3D integration, interposers, HBM,