Lead Package Design Architect – HPC Datacenter

QUALCOMM, Inc.; San Diego (CA); On-site; USD 210,000 - 315,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a senior leader to guide the CHS Datacenter package design team, driving end‑to‑end architecture for high‑performance compute products.

You will own technology roadmaps, coordinate with silicon, platform, and manufacturing teams, and ensure performance, power, and cost targets are met. The role emphasizes deep expertise in multi‑chiplet packaging, HBM, silicon interposers, and high‑density substrates, with a focus on scalable design methodologies and executive

Qualifications

• Proven leadership of package design teams and capability building.
• Deep expertise in multi‑die packaging and AI/HPC/server contexts.
• Strong system-level view of chip‑package‑board interactions.
• Ability to translate performance, power, and thermal goals into package requirements.

Responsibilities

• Lead CHS Datacenter package design team and mentor staff.
• Own end‑to‑end advanced package architecture strategy for HPC products.
• Drive 2.5D/3D integration and interposer decision making.
• Oversee die placement, routing, power delivery, and board escape.
• Coordinate with silicon, platform, and manufacturing teams to meet targets.
• Define design rules and release processes with cross‑functional partners.

Skills

Leadership

Advanced packaging

2.5D/3D integration

System-level analysis

Cross-functional leadership

Si design knowledge

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Cadence APD/SiP

PowerSI

HFSS

Xpedition Package Designer

Calibre

Job description

Qualcomm Technologies, Inc. seeks a senior leader to guide the CHS Datacenter package design team, driving end‑to‑end architecture for high‑performance compute products.

You will own technology roadmaps, coordinate with silicon, platform, and manufacturing teams, and ensure performance, power, and cost targets are met. The role emphasizes deep expertise in multi‑chiplet packaging, HBM, silicon interposers, and high‑density substrates, with a focus on scalable design methodologies and executive