Advanced Package Design Engineer – Principal Engineer

Qualcomm; San Diego (CA); On-site; USD 210,000 - 315,000; Full time

Benefits offered by this job

Bonus program

RSU grants

Competitive benefits

Job summary

Qualcomm Technologies, Inc. in San Diego, CA, seeks a Principal Engineer to build and lead a 2.5D/3D Advanced Package Design team for HPC and Datacenter products.

You will own scalable design methodologies, flows, and production‑quality signoff for multi‑die packages, collaborating with foundries, EDA vendors, OSATs, and internal teams. The ideal candidate combines hands‑on interposer, chiplet, HBM, and substrate design expertise with a successful track record building and growing engineering

Qualifications

• Proven track record of leading advanced package design teams.
• Deep expertise in 2.5D/3D integration and HBM/chiplet architectures.
• Experience deploying production 2.5D/3D design flows and signoff.
• Strong collaboration with foundries, OSATs, and EDA vendors.

Responsibilities

• Build and grow a high‑performing 2.5D/3D package design team.
• Own strategy, roadmap, and deployment of end‑to‑end design flows.
• Develop scalable flows for die/chiplet assembly, floorplanning, and interposer design.
• Lead 2.5D/3D package implementations using interposers, bridges, and HBMs.
• Align toolchains with Cadence, Siemens EDA, Synopsys, and others; ensure repeatability.

Skills

Advanced packaging design

3DIC

EDA tools experience

Leadership

Communication

Education

Bachelor's in Electrical/Mechanical/Chemical Eng

Master's or PhD preferred

Tools

Cadence

Siemens EDA

Synopsys

Ansys

3DIC tools

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > Packaging Engineering

General Summary:

We are seeking a Principal Engineer to build and lead a 2.5D/3D Advanced Package Design team within CHS, supporting next-generation high-performance compute (HPC) and Datacenter products. This leader will own the development, deployment, and continuous improvement of scalable 2.5D/3D package design methodologies and flows, while also directing package architecture, design implementation, verification, and release for complex multi-die products.

The ideal candidate combines deep hands‑on expertise in silicon‑interposer, silicon‑bridge, chiplet, HBM, and advanced substrate design with a proven record of developing engineering teams and production‑quality design flows. The individual will evaluate and integrate industry EDA and foundry ecosystems, including standards and frameworks such as TSMC 3Dblox, and will partner with EDA vendors, foundries, OSATs, substrate suppliers, and internal engineering teams to establish robust, automated, and signoff‑ready design solutions. This position requires strategic leadership, strong technical credibility, and the ability to translate emerging 2.5D/3D technologies into repeatable product execution.

Role and Responsibilities:

• Build, manage, mentor, and grow a high-performing 2.5D/3D advanced package design team consisting of package architects, physical‑design engineers, methodology developers, CAD/automation engineers, and technical leads.
• Own the strategy, roadmap, architecture, implementation, qualification, and deployment of end-to-end 2.5D/3D package design methodologies and flows for complex multi-die products.
• Develop standardized, scalable, and reusable flows spanning early package planning, die/chiplet assembly definition, floorplanning, HBM and chiplet placement, bump and interface planning, interposer/bridge design, substrate design, package verification, signoff, tapeout, and release.
• Lead implementation of 2.5D/3D packages using silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, hybrid‑bonded or vertically stacked die, HBM, and other emerging integration technologies.
• Evaluate and deploy foundry and EDA‑vendor 3DIC solutions, including TSMC 3Dblox-compatible methodologies and interoperable implementation, analysis, verification, data‑exchange, and signoff flows.
• Define tool requirements and drive technical alignment with Cadence, Siemens EDA, Synopsys, Ansys, foundries, and other ecosystem partners to close capability gaps and improve design productivity, quality, and scalability.
• Establish design‑flow architecture, data models, interfaces, automation frameworks, configuration management, regression testing, release management, metrics, documentation, and user support for production package design.
• Guide package architecture and physical implementation across die/chiplet floorplanning, bump maps, HBM placement, die-to-die interfaces, package connectivity, routing topology, layer‑stack optimization, power/ground distribution, board escape, and package-size optimization.
• Define and govern package verification and signoff requirements, including connectivity, DRC, DFM, ERC, LVS‑equivalent checks, assembly‑rule compliance, package extraction, SI/PI, thermal, mechanical, reliability, and manufacturability reviews.
• Partner with silicon architecture, SoC physical design, DFT, SI/PI, thermal, mechanical, board, product engineering, manufacturing, and supply‑chain teams to enable concurrent chip‑package‑board‑system co‑design.
• Lead package design execution from feasibility through tapeout and production release; establish design reviews, technical checkpoints, risk tracking, escalation paths, and closure criteria across product programs.
• Drive methodology correlation and validation using representative test cases and product designs; ensure flow readiness, repeatability, traceability, and robustness before broad production adoption.
• Engage foundries, OSATs, substrate suppliers, and assembly partners to understand technology structures, process constraints, design rules, assembly requirements, test considerations, reliability risks, yield limiters, and production‑readiness requirements.
• Develop team capability plans, hiring profiles, training, succession plans, and technical career paths; coach senior engineers and establish subject‑matter experts for key 2.5D/3D design domains.
• Represent advanced package design in executive and program reviews, communicating roadmap decisions, architecture tradeoffs, methodology readiness, resource requirements, execution status, technical risks, and mitigation plans.

Skills:

• Proven experience building and leading advanced package design, 3DIC methodology, package CAD, or physical‑design teams, including hiring, mentoring, performance development, resource planning, and technical‑lead development.
• Deep knowledge of 2.5D/3D integration technologies and structures, including silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, HBM integration, chiplets, die stacking, micro‑bumps, hybrid bonding, and package assembly.
• Hands‑on experience defining or deploying production 2.5D/3D design flows covering planning, implementation, verification, multi‑physics analysis, design‑data handoff, tapeout, and release.
• Understanding of industry 3DIC EDA ecosystems and foundry design enablement, including TSMC 3Dblox concepts, die/package assembly description, hierarchy, connectivity, constraints, design reuse, and cross‑tool interoperability.
• Expertise with relevant package and 3DIC implementation environments from Cadence, Siemens EDA, Synopsys, or equivalent vendors; strong understanding of constraint management, database integration, automation, and signoff.
• Expert knowledge of advanced package physical design, including multi‑die floorplanning, HBM placement, bump and interface planning, pinout optimization, high‑density routing, interposer/bridge implementation, substrate stackup, power/ground planning, and board escape.
• Strong understanding of package‑level SI/PI and electromagnetic effects for HBM, UCIe and other die‑to‑die interfaces, PCIe, DDR, high‑speed SerDes, clocks, and high‑current power delivery.
• Working knowledge of package thermal‑mechanical and reliability analysis, including warpage, die/interposer stress, material interactions, thermal interfaces, assembly process windows, failure mechanisms, and qualification requirements.
• Experience establishing DRC, DFM, ERC, connectivity, extraction, multi‑physics, and release‑signoff methodology using foundry, OSAT, substrate, and internal rules.
• Strong scripting and automation mindset, with experience developing maintainable flows using languages and environments such as Python, Tcl, Perl, shell, APIs, workflow orchestration, regression systems, and version control.
• Ability to assess EDA tool capability, benchmark competing solutions, define requirements, drive vendor roadmaps, resolve tool and methodology gaps, and establish production‑support models.
• Excellent executive communication, technical decision‑making, cross‑functional influence, supplier engagement, and ability to lead globally distributed teams through complex, ambiguous engineering challenges.

Preferred Qualifications:

• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science, or a related field, with 15+ years of semiconductor package design, 3DIC, physical‑design methodology, or related experience; equivalent industry experience may be considered.
• Demonstrated record of building and managing a substantial advanced package design or methodology organization supporting multiple complex products and technology generations.
• Proven ownership of production 2.5D/3D package design methodology and implementation for AI, HPC, Datacenter, accelerator, networking, or other high‑performance multi‑die products.
• Direct experience delivering packages that integrate compute SoCs or chiplets with HBM using silicon‑interposer, silicon‑bridge, RDL‑interposer, or vertically integrated 3D solutions.
• Experience integrating foundry reference flows and assembly‑description frameworks such as TSMC 3Dblox into internal design, analysis, verification, and tapeout environments.
• Extensive experience with industry‑leading 2.5D/3D IC design, implementation, and verification environments, including Cadence Innovus, Integrity 3D-IC, Allegro Package Designer (APD), Virtuoso, Siemens Calibre 3DSTACK, and comparable Synopsys and Ansys 3DIC solutions.
• Demonstrated experience evaluating, integrating, and deploying multi‑vendor EDA tools within foundry‑qualified 2.5D/3D design flows, including familiarity with assembly‑description and interoperability frameworks such as TSMC 3Dblox.
• Experience establishing cross‑domain chip‑package‑board co‑design and multi‑physics workflows spanning electrical, thermal, mechanical, reliability, test, manufacturing, and system constraints.
• Experience working directly with leading foundries, OSATs, substrate suppliers, assembly partners, EDA vendors, and IP providers to evaluate, develop, validate, qualify, and ramp advanced packaging solutions.
• Understanding of HBM, UCIe or other die‑to‑die protocols, PCIe, DDR, and high‑speed SerDes, including package architecture, layout, extraction, SI/PI, and verification implications.
• Demonstrated ability to define methodology roadmaps, prioritize investments, establish measurable design‑flow quality and productivity targets, and drive deployment across a global engineering organization.
• Demonstrated innovation through advanced package solutions, EDA methodologies, automation, patents, publications, industry working groups, or standards engagement is highly desirable.

Minimum Qualifications:

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience.
• Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 7+ years of System/Package Design/Technology Engineering or related work experience.
• PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ year of System/Package Design/Technology Engineering or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$210,000.00 - $315,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.