Senior Formal Verification Engineer – ASIC SoC

Etched.ai, Inc.; San Jose, Northern (CA, KY); Hybrid; USD 160,000 - 260,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Housing subsidy $2.5k per month near办公

Relocation support to San Jose (SantNa

Job summary

Etched.ai, Inc. is seeking a Formal Verification Engineer to drive formal verification across custom IP, interface IP, and SoC subsystems for our ASICs in San Jose. You will collaborate with architects, RTL designers, and DV teams to prove design correctness and uncover deep corner-case bugs.

The role focuses on formal properties, proof convergence, and sign-off methodologies to advance verification closure in a fast-paced startup environment.

Qualifications

• 5+ years of design verification experience, including formal verification on complex digital designs.

Responsibilities

• Define and drive formal verification strategy across the ASIC DV team.
• Develop formal plans covering functional correctness, connectivity, ordering, reset behavior.
• Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, and reference models.
• Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics.
• Translate design intent and specifications into high-value formal properties and closure criteria.
• Partner with DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.
• Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.
• Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

Skills

SystemVerilog

SystemVerilog Assertions

Formal verification methodology

Debugging

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens Questa Formal

Job description

Etched.ai, Inc. is seeking a Formal Verification Engineer to drive formal verification across custom IP, interface IP, and SoC subsystems for our ASICs in San Jose. You will collaborate with architects, RTL designers, and DV teams to prove design correctness and uncover deep corner-case bugs.

The role focuses on formal properties, proof convergence, and sign-off methodologies to advance verification closure in a fast-paced startup environment.