Principal Formal Verification Engineer

Acceler8 Talent; Mountain View (CA); Vor Ort; USD 140.000 - 190.000; Vollzeit

Zusammenfassung

Acceler8 Talent is seeking a Formal Verification Engineer to lead the verification strategy for AI accelerator silicon in Mountain View, CA. You will own block- and SoC-level formal verification from architecture through bring-up, crafting SVA/PSL properties and robust verification environments.

You will debug complex proof failures with RTL teams, refine methodologies, and push AI-assisted verification workflows to drive faster convergence and higher confidence in silicon correctness.

Qualifikationen

• Master's degree (or equivalent) plus 8+ years of formal verification experience for complex SoCs.
• Deep expertise in formal verification methodologies, including property authoring (SVA/PSL), proof strategies, abstraction techniques, and convergence.
• Strong experience debugging formal failures and collaborating with RTL designers to resolve issues.
• Hands-on experience with industry-standard formal verification tools such as VC Formal, JasperGold, or equivalent.
• Strong understanding of modern digital design and microarchitecture.

Aufgaben

• Own block- and SoC-level formal verification for AI accelerator silicon, from property development through proof convergence.
• Develop SystemVerilog Assertions (SVA) and formal verification environments to verify complex microarchitectural and system-level behavior.
• Debug proof failures, identify root causes, and collaborate with RTL designers and architects to drive closure.
• Build and improve formal verification methodologies, infrastructure, and AI-assisted verification flows, including AI agents that accelerate proof generation and convergence.
• Apply formal techniques throughout the development cycle, from early architectural validation through silicon bring-up readiness.
• Partner closely with design, verification, and software teams to ensure robust, scalable hardware.

Kenntnisse

Formal verification

SVA/PSL

Proof strategies

Convergence

Debugging failures

Ausbildung

Master's degree or equivalent

Tools

Synopsys VC Formal

Cadence JasperGold

Jobbeschreibung

Formal Verification Engineer

Location: Mountain View, CA (Onsite)

Acceler8 Talent is partnering with an early-stage AI hardware startup to hire a Formal Verification Engineer to help redesign AI datacenter infrastructure and silicon.

As the first Formal Verification hire, you'll own the formal verification strategy for critical blocks and SoC-level functionality, proving correctness on complex hardware while helping shape verification methodologies from first silicon through future generations of our platform. You'll work closely with architecture, RTL, and software teams, and have the opportunity to leverage cutting-edge AI-assisted verification workflows to solve problems that don't have established playbooks.

What You'll Do:

• Own block- and SoC-level formal verification for AI accelerator silicon, from property development through proof convergence.
• Develop SystemVerilog Assertions (SVA) and formal verification environments to verify complex microarchitectural and system-level behavior.
• Debug proof failures, identify root causes, and collaborate with RTL designers and architects to drive closure.
• Build and improve formal verification methodologies, infrastructure, and AI-assisted verification flows, including AI agents that accelerate proof generation and convergence.
• Apply formal techniques throughout the development cycle, from early architectural validation through silicon bring-up readiness.
• Partner closely with design, verification, and software teams to ensure robust, scalable hardware.

What They're Looking For:

• Master's degree (or equivalent experience) plus 8+ years of experience in formal verification for complex SoCs.
• Deep expertise in formal verification methodologies, including property authoring (SVA and/or PSL), proof strategies, abstraction techniques, and convergence.
• Strong experience debugging formal failures and working directly with RTL designers to resolve issues.
• Hands-on experience with industry-standard formal verification tools such as Synopsys VC Formal, Cadence JasperGold, or equivalent.
• Strong understanding of modern digital design and microarchitecture.

Nice to Have:

• Experience with processor verification or security verification.
• Equivalence checking (LEC/SEC) experience.
• AMS verification or IP verification flow experience.
• Experience building automation or AI-assisted verification workflows.

Why Join?

• Own verification for critical AI accelerator hardware at an early-stage company.
• Work on technically ambitious silicon with significant architectural influence.
• Help define next-generation AI-assisted formal verification methodologies.
• Collaborate with a small, highly experienced team building cutting-edge AI infrastructure from the ground up.