Senior Formal Verification Engineer, AI Silicon

Architect Labs; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity stake

Autonomy & impact

Frontier AI & silicon

Job summary

Architect Labs is seeking a Member of Technical Staff - Formal Verification Engineer to own formal verification from specs to tape-out. You will turn design intent into assertions, build formal environments, and work directly with designers to verify complex designs.

You will develop verification plans, build formal testbenches, drive proofs to completion, and collaborate with AI researchers to integrate formal methods into the design flow.

Qualifications

• BS or MS in EE/CE/CS or equivalent practical experience.
• Strong SystemVerilog and SVA skills; read RTL and write properties.
• Hands-on with Cadence Jasper, VC Formal or Questa Formal.
• Knowledge of model checking, induction, abstraction and assume–guarantee reasoning.
• Hardware understanding of control logic, pipelines and interfaces.
• Strong scripting in Python or Tcl; automate workflows.
• Ownership: work from incomplete specs and meet tape-out deadlines.

Responsibilities

• Develop and execute formal verification plans for hardware blocks and subsystems.
• Build Spec to SVA flows with test plans and formal testbenches.
• Drive proofs to completion using abstraction and solver strategies.
• Debug counterexamples and collaborate with RTL designers to fix issues.
• Assess verification completeness; document proven vs open items.
• Create reusable verification components and automate regressions.

Education

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Jasper

Synopsys VC Formal

Questa Formal

UVM

Job description

Architect Labs is seeking a Member of Technical Staff - Formal Verification Engineer to own formal verification from specs to tape-out. You will turn design intent into assertions, build formal environments, and work directly with designers to verify complex designs.

You will develop verification plans, build formal testbenches, drive proofs to completion, and collaborate with AI researchers to integrate formal methods into the design flow.