Lead DRAM Design Engineer – Memory Architect

Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Job summary

Micron Technology, Inc. seeks a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept through silicon validation. You will lead design decisions that affect performance, power, and reliability while collaborating with cross-functional teams to deliver scalable memory solutions.

The role emphasizes hands-on circuit design, SPICE/Verilog simulations, and close alignment with layout and test initiatives across various technology nodes.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 2+ years of circuit design experience or 4+ years of product engineering experience.
• Strong understanding of analog and digital circuit fundamentals and debugging.
• Experience with circuit simulation tools and methodologies.
• Knowledge of CMOS behavior, timing, and performance optimization.

Responsibilities

• Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic.
• Perform and analyze circuit simulations using tools such as SPICE and Verilog.
• Evaluate architectural trade-offs impacting power, performance, and die size.
• Integrate layout parasitics into simulations and drive design for manufacturability.
• Define validation strategies including test chip development and silicon bring-up.

Skills

Circuit design

Analog and digital fundamentals

Circuit simulation

CMOS timing

Education

Bachelor's degree in Electrical Engineering

Tools

SPICE

Verilog

Job description

Micron Technology, Inc. seeks a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept through silicon validation. You will lead design decisions that affect performance, power, and reliability while collaborating with cross-functional teams to deliver scalable memory solutions.

The role emphasizes hands-on circuit design, SPICE/Verilog simulations, and close alignment with layout and test initiatives across various technology nodes.