Staff DRAM Design Engineer — Memory & ASIC Innovation

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plans (vision/dental)

Paid family leave

Generous paid time off & holidays

Job summary

Micron Technology seeks an experienced engineer to design and optimize memory-related circuits across digital and analog domains. The role involves parasitic modeling, layout oversight, and rigorous verification using standard simulators.

The ideal candidate has a strong background in CMOS/VLSI and hands-on mixed-signal design, with familiarity in tape-out flows and parasitic analysis. Collaboration across cross-functional teams is essential to ensure robust manufacturability.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 5 years of experience in CMOS and VLSI circuit design across digital and analog domains.
• Hands-on mixed-signal design experience, including schematic design, layout, and circuit simulation using industry-standard tools.
• Experience with power distribution design, parasitic modeling, and tape-out flows.

Responsibilities

• Design, lay out, and optimize memory, logic, and analog circuits for new memory products.
• Handle parasitic modeling and support design validation, reticle experiments, and tape-out revisions.
• Oversee the layout process, including floor-planning, placement, and routing.
• Run verification through modeling and simulation using industry-standard simulators.
• Partner with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering to ensure manufacturability, and use generative AI tools to speed up design, analysis, and documentation while owning correctness and sign-off.

Skills

CMOS & VLSI circuit design

Digital & analog design

Mixed-signal design

Schematic design

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence

SPICE simulators

Job description

Micron Technology seeks an experienced engineer to design and optimize memory-related circuits across digital and analog domains. The role involves parasitic modeling, layout oversight, and rigorous verification using standard simulators.

The ideal candidate has a strong background in CMOS/VLSI and hands-on mixed-signal design, with familiarity in tape-out flows and parasitic analysis. Collaboration across cross-functional teams is essential to ensure robust manufacturability.