DPU IO Architect, Infrastructure Silicon

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking a Data Processing Unit (DPU) IO Architect to own the I/O subsystem, PCIe, DMA, offload engines, and I/O virtualization for DPUs and NICs. You will define register and programming models, interfaces, and how hardware, firmware, and software interact.

You will work with firmware, driver, and RTL teams from early design through silicon bring-up. You will evaluate performance, power, and area trade-offs, drive architectural decisions with data, and help define DV-friendly features.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8+ years architecting I/O and system subsystems with hardware/software interfaces.
• Experience with PCIe data link protocols and TLP formats.
• Experience with I/O virtualization technologies such as SR-IOV/SIOV.
• Experience with PCIe capabilities like AER, Downstream Port Containment, and encryption.
• Experience with on-chip scheduling, QoS mechanisms, and latency/bandwidth tradeoffs.
• Experience with cryptography concepts and inline data encryption.
• Experience with x86/ARM architecture, virtualization, IOMMUs, and interrupt virtualization.
• Experience with data center workloads and I/O characteristics.
• Ability to drive architectural decisions independently and data-driven.

Responsibilities

• Own the I/O subsystem architecture for DPUs including PCIe, DMA, offload engines, I/O virtualization, confidential computing, and system management.
• Decide what runs in hardware vs firmware vs host software and design interfaces between them.
• Define hardware/software interface models, descriptors, and offload interfaces for firmware and drivers.
• Collaborate closely with firmware, driver, and software teams to keep interfaces clean and usable.
• Back decisions with performance data and trading off power, area, and performance.
• Coordinate with design, DV, and PD teams on feature definition and PPA tradeoffs.
• Refine architecture to meet design and PD constraints and ease DV complexity.
• Support post-silicon bring-up of the I/O subsystem and resolve interface issues.

Skills

DPU IO Architecture

PCIe & DMA interfaces

I/O virtualization

Hardware-software interface design

Register/Programming models

Offload interfaces

Performance/PPA tradeoffs

System architecture (x86/ARM)

Confidential Computing concepts

Data center IO characterization

Education

Bachelor's degree in Computer Science or Computer Engineering

PhD in Computer Science/Engineering (preferred)

Tools

SystemVerilog

VHDL

Python

Simulation environments

Job description

Summary:

Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs.We are looking for a Data Processing Unit (DPU) I/O Architect to own the I/O subsystem and the hardware/software interface between our silicon and the software that drives it - PCIe, DMA and offload engines, I/O virtualization, Confidential Computing, and system management. You'll define how the hardware presents itself to firmware and software - the register and programming models, descriptor and doorbell interfaces, and offload interfaces - and decide what belongs in hardware versus firmware versus software. You'll work hand in hand with the firmware, driver, and RTL teams, and carry your designs from early path-finding through implementation and silicon bring-up.

Required Skills:

DPU IO Architect, Infrastructure Silicon Responsibilities:

1. Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up

2. Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them

3. Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on

4. Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change

5. Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed

6. Work closely with design, DV, and PD teams on feature definition and PPA tradeoff

7. refine architecture to meet the design and PD constraints. Define architecture to maximize DV complexity including defining specific features to help ease DV

8. Support Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the I/O subsystem

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs

3. Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules

4. Experience with I/O virtualization technologies such as SR-IOV and SIOV

5. Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption

6. Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput

7. Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM)

8. Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization

9. Experience with data center workloads and their I/O characteristics

10. Experience driving architectural decisions independently and influencing their direction through data

Preferred Qualifications:

1. PhD in Computer Science, Computer Engineering or Electrical Engineering

2. 15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs

3. Experience designing PCIe endpoints and root complexes

4. Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows

5. Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis

6. Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs

7. Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI

8. Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression

9. Experience with post-silicon performance validation and model-to-hardware correlation methodologies

10. Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affinitative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].