DPU IO Architect, Infrastructure Silicon

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta’s Infrastructure Silicon organization builds custom silicon powering data center infrastructure, including SmartNICs/IPUs/DPUs and AI accelerators. We seek a DPU I/O Architect to own the I/O subsystem, defining interfaces between hardware, firmware and software.

You’ll collaborate with firmware, driver and RTL teams, choosing what belongs where and driving the design through bring-up with data-driven decisions.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 8+ years of experience architecting I/O and system subsystems for NIC/DPU or similar ASICs.
• Experience with PCIe, I/O virtualization, and DMA/descriptor interfaces.
• Experience with cryptography concepts and on-chip security interfaces.

Responsibilities

• Own the I/O subsystem architecture for DPUs, including PCIe, DMA, I/O virtualization, confidential computing, and system management.
• Decide what runs in hardware vs firmware vs host software and design interfaces.
• Define hardware/software interfaces: register models, descriptor/doorbell interfaces, error/interrupt models.
• Work with firmware, driver, and software teams to keep interfaces clean and usable.
• Weigh performance, power, and area trade-offs with data-backed analysis.
• Collaborate with design, DV, and PD teams on feature definition and PPA trade-offs.
• Refine architecture to meet design constraints and ease DV.
• Support post-silicon bring-up and resolve interface/integration issues.

Skills

I/O architecture

PCIe DMA interfaces

I/O virtualization

Architecture decisions

Performance trade-offs

Data center workloads

Education

Bachelor's degree in CS/CE or equivalent

PhD in CS/CE/EE (preferred)

Tools

SystemVerilog

VHDL

Python

Job description

Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs.We are looking for a Data Processing Unit (DPU) I/O Architect to own the I/O subsystem and the hardware/software interface between our silicon and the software that drives it - PCIe, DMA and offload engines, I/O virtualization, Confidential Computing, and system management. You'll define how the hardware presents itself to firmware and software - the register and programming models, descriptor and doorbell interfaces, and offload interfaces - and decide what belongs in hardware versus firmware versus software. You'll work hand in hand with the firmware, driver, and RTL teams, and carry your designs from early path-finding through implementation and silicon bring-up.

DPU IO Architect, Infrastructure Silicon Responsibilities:

• Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up
• Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them
• Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on
• Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change
• Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed
• Work closely with design, DV, and PD teams on feature definition and PPA tradeoff
• refine architecture to meet the design and PD constraints. Define architecture to maximize DV complexity including defining specific features to help ease DV
• Support Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the I/O subsystem

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs
• Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules
• Experience with I/O virtualization technologies such as SR-IOV and SIOV
• Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption
• Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput
• Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM)
• Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization
• Experience with data center workloads and their I/O characteristics
• Experience driving architectural decisions independently and influencing their direction through data

Preferred Qualifications:

• PhD in Computer Science, Computer Engineering or Electrical Engineering
• 15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs
• Experience designing PCIe endpoints and root complexes
• Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows
• Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis
• Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs
• Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI
• Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression
• Experience with post-silicon performance validation and model-to-hardware correlation methodologies
• Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

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$178,000/year to $250,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.