Lead Digital IC Engineer (RTL/Verilog)

SmartRecruiters, Inc.; Duluth (GA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics in the United States seeks an experienced ASIC/IC design engineer to architect and design RTL in Verilog for a mixed-signal IC. You will work within a senior team on clocking controls, FSM design, low power techniques, and high-speed concepts for advanced silicon.

The role entails participating in design, architecture, and verification reviews, and supervising the digital backend, including synthesis, STA, and LEC.

Qualifications

• Education: Bachelor or Master in Electrical/ECE/CS or related field with 12+ years of experience.
• 8+ years direct ASIC/IC design experience.
• Fluent in Verilog RTL coding and ASIC design methodology.
• Expertise in digital design implementation including synthesis and DFT insertion with high coverage.
• Experience with static timing analysis and creation of place and route constraints.
• Proficiency in formal verification, linting, and CDC/RDC checking.
• Knowledge of asynchronous clock crossings and RTL synthesis implications.
• Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists.
• Developing design constraints for synthesis, STA, and P&R hand-off.
• Experience with gate-level simulations and timing violation analysis.

Responsibilities

• Participate in design, architecture, and verification reviews.
• Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking.
• Create documentation targeting design, verification, and test teams.
• Assist with proposal, definition, documentation, and implementation of new features.
• Mentor and train junior engineers and New College Grad engineers.

Skills

Verilog RTL coding

ASIC design

Digital design

Synthesis

Static timing analysis

DFT insertion

Formal verification

Linting

CDC/RDC checking

Clocking controls

Education

Bachelor's or Master's degree in Electrical Engineering/Computer Engineering/Computer Science

Job description

Renesas Electronics in the United States seeks an experienced ASIC/IC design engineer to architect and design RTL in Verilog for a mixed-signal IC. You will work within a senior team on clocking controls, FSM design, low power techniques, and high-speed concepts for advanced silicon.

The role entails participating in design, architecture, and verification reviews, and supervising the digital backend, including synthesis, STA, and LEC.