Senior RTL Digital Design Engineer – Memory Interfaces

Renesas Electronics; Duluth (GA); Hybrid; USD 120,000 - 230,000; Full time

Benefits offered by this job

Remote work option

Employee Resource Groups

Diversity & Inclusion initiatives

Job summary

Renesas Electronics seeks a senior engineer to design RTL in Verilog for memory data buffer chips used in DDR5/DDR6, supporting data centers and AI workloads. You will work on digital sections of high-performance devices and contribute across architecture, verification, and backend implementation.

The role requires 12+ years in ASIC/IC design, deep RTL expertise, and hands-on experience with synthesis, STA, DFT, and formal methods.

Qualifications

• 12+ years of direct ASIC/IC design experience.
• Deep knowledge of the full IC design flow.
• Fluent in Verilog RTL coding and ASIC methodologies.
• Experience with Synthesis, STA, DFT, and CDC/RDC checking.

Responsibilities

• Propose, architect, and design RTL in Verilog for mixed-signal IC.
• Oversee digital backend design including synthesis, STA, and LEC.
• Participate in design reviews and mentor junior engineers.
• Create documentation for design, verification, and test teams.

Skills

Verilog RTL coding

ASIC/IC design

Synthesis, STA, P&R

DFT insertion

Formal verification

Clocking, timing analysis

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

EDA tools (Verilog/VHDL)

Job description

Renesas Electronics seeks a senior engineer to design RTL in Verilog for memory data buffer chips used in DDR5/DDR6, supporting data centers and AI workloads. You will work on digital sections of high-performance devices and contribute across architecture, verification, and backend implementation.

The role requires 12+ years in ASIC/IC design, deep RTL expertise, and hands-on experience with synthesis, STA, DFT, and formal methods.