Senior Digital DFT Design Engineer for Automotive PMIC

Renesas Electronics; Arizona; On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

Renesas Electronics is seeking a senior DFT/RTL design professional to join our Automotive PMIC team in the United States. You will drive scan insertion, ATPG, and LogicBIST across complex digital blocks, collaborating with designers, test, and silicon teams to meet ASIL-B/D requirements.

The role requires deep RTL experience, formal DFT expertise, and a track record with multiple tapeouts. On-site collaboration and rigorous design reviews are essential to success.

Qualifications

• Masters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT.
• </br>Must be a team player with strong digital design and DFT fundamentals.
• </br>Hands-on experience in Scan insertion, improving scan coverage, ATPG, RTL-level DFT.

Responsibilities

• Insert DFT/Scan on digital logic and validate test patterns on silicon.
• Deliver test patterns to TEST engineering and validate them.
• Insert LogicBIST with industry-standard tools during synthesis/RTL.
• Improve scan coverage and modify RTL for scan.
• Reduce ATE tester time by optimizing scan patterns while maintaining coverage.
• Collaborate with Architects, Design, P&R, Test and Silicon validation teams.
• Assist with top-level test-bench creation for scan and run gate-level simulations.
• Debug scan pattern fails on ATE and fix patterns.
• Write design docs and DFT specs and lead design reviews.

Skills

DFT/Scan insertion

ATPG

LogicBIST

RTL Verilog/SystemVerilog

Timing constraints

Synthesis

Digital design

Simulation

Education

BSEE

MSEE preferred

Tools

Synopsys

Cadence

Mentor

Siemens

Tetramax

Job description

Renesas Electronics is seeking a senior DFT/RTL design professional to join our Automotive PMIC team in the United States. You will drive scan insertion, ATPG, and LogicBIST across complex digital blocks, collaborating with designers, test, and silicon teams to meet ASIL-B/D requirements.

The role requires deep RTL experience, formal DFT expertise, and a track record with multiple tapeouts. On-site collaboration and rigorous design reviews are essential to success.