Senior Digital Design Architect - Low-Power Mixed-Signal

Renesas Electronics; Chandler (AZ); On-site; USD 140,000 - 200,000; Full time

Job summary

Renesas Electronics seeks a Staff Digital Design Engineer to join our Chandler hardware team in Chandler, AZ. You will design power- and area-optimized digital circuits for complex mixed-signal applications, and lead RTL and verification efforts to meet timing and power targets.

You will collaborate with Analog, Verification and P&R teams, mentor junior engineers, and contribute to design reviews and documentation throughout the silicon development lifecycle.

Qualifications

• ≥10 years of digital design experience in wireless, data conversion or power management.
• Degree in Electrical/Electronics/CE/CS or related field.
• Fluent in Verilog/SystemVerilog RTL for digital CMOS.
• Willingness to travel domestically or internationally.

Responsibilities

• Architect and design low-power digital circuits for mixed-signal products.
• Lead RTL/verification efforts and drive timing, area and power goals.
• Collaborate with P&R, DFT, and verification teams throughout the flow.
• Mentor junior engineers and contribute to design reviews.
• Develop and maintain design documentation and collateral.
• Support pre-silicon verification and top-level simulations.

Skills

Digital design

Verilog/SystemVerilog

Low-power design

RTL/Timing closure

Technical leadership

Education

Electrical/Electronics/CE/CS degree

Tools

Verilog

SystemVerilog

UPF

UVM

Job description

Renesas Electronics seeks a Staff Digital Design Engineer to join our Chandler hardware team in Chandler, AZ. You will design power- and area-optimized digital circuits for complex mixed-signal applications, and lead RTL and verification efforts to meet timing and power targets.

You will collaborate with Analog, Verification and P&R teams, mentor junior engineers, and contribute to design reviews and documentation throughout the silicon development lifecycle.